MCZ33298EGR2 Freescale, MCZ33298EGR2 Datasheet - Page 16

• Manufacturer Part Number: MCZ33298EGR2
• Manufacturer: Freescale

Specifications of MCZ33298EGR2

• Switch Type: Low Side
• Power Switch Family: MCZ33298
• Input Voltage: -0.3 to 7V
• Power Switch On Resistance: 400mOhm
• Output Current: 1A
• Number Of Outputs: 8
• Mounting: Surface Mount
• Supply Current: 1uA
• Package Type: SOIC W
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Power Dissipation: 3W
• Lead Free Status / RoHS Status: Compliant

care should be taken to not transition SI as SCLK transitions
from a low-to-high logic state.
SERIAL OUTPUT (SO)
the Shift register. The SO pin remains in a high-impedance
state until the CS pin goes to a logic low state. The SO data
reports the drain status, either high or low relative to the
previous command word. The SO pin changes state on the
rising edge of SCLK and reads out on the falling edge of
SCLK. When an output is OFF and not faulted, the
corresponding SO data-bit is a high state. When an output is
ON, and there is no fault, the corresponding data-bit on the
SO pin will be a low logic state. The SI/SO shifting of data
follows a first-in-first-out (FIFO) protocol with both input and
output words transferring the MSB first. Referring to
Figure
relative to the previous command word. The SO pin is not
affected by the status of the Reset pin.
RESET (RST)
the SPI Shift register. In doing so, all output switches are set
at OFF. The device situated in the same system with an
MCU, the MCU retains the Reset pin of the device in a logic
low state. Retention ensures all outputs to be OFF until both
the VDD and VPWR pin voltages are adequate for
predictable operation. Retention of the device RST pin takes
place only upon initial system power up. After the 33298 is
reset, the MCU is ready to assert system control with all
output switches initially OFF.
following normal operation, the MCU should pull the RST pin
low to shutdown the outputs and clear the input data register.
The RST pin is active low and has an internal pull-down
incorporated, insuring operational predictability should the
external pull-down of the MCU open circuit. The internal pull-
down is only 25µA, affording safe and easy interfacing to the
MCU. The Reset pin of the 33298 should be pulled to a logic
low state for a duration of at least 250ns, ensuring reliable a
reset.
programmed through the use of an RC network comprised of
a shunt capacitor from the RST pin to Ground and a resistor
to VDD, illustrated in
ensuring proper discharge of the capacitor. Careful attention
eliminates adverse delay of the Reset and damage of the
MCU if it pulls the Reset line low, thereby accomplishing
initialization for turn ON delay. It may be easier to incorporate
delay into the software program and use a parallel port pin of
the MCU to control the 33298 RST pin.
16
33298
FUNCTIONAL DESCRIPTION
INTRODUCTION
The serial output (SO) pin is the tri-stateable output from
The 33298 reset (RST) pin is active low. It is used to clear
If the VPWR pin of the 33298 experiences a low voltage,
A simple power ON reset delay of the system can be
18, the DO bit is the MSB corresponding to Output 7
Figure
17. Care should be exercised
SHORT FAULT PROTECT DISABLE (SFPD)
prevent the outputs from latching-off due to an over-current
condition. This feature provides control of incandescent lamp
loads where in-rush currents exceed the device’s analog
current limits. Essentially the SFPD pin determines whether
the 33298 output(s) will instantly shutdown upon sensing an
output short or remain ON in a current limiting mode of
operation until the output short is removed or thermal
shutdown is reached. If the SFPD pin is tied to V
the 33298 output(s) will remain ON in a current limited mode
of operation upon encountering a load short to supply or over-
current condition. When the SFPD pin is grounded, a short-
circuit will immediately shut down only the output affected.
Other outputs not having a fault condition will operate
normally. The short-circuit operation is addressed in more
detail later.
POWER CONSUMPTION
the operating and standby modes. In the standby, or Sleep
mode, with V
pin is less than 25µA. In the operating mode, the current
drawn by the VDD pin is less than 4.0mA (1.0mA typical)
while the current drawn at the VPWR pin is 2.0mA maximum
(1.0mA typical). During normal operation, turning outputs ON
increases I
experiencing a soft short (over-current conditions just under
the current limit), adds 0.5mA to the I
PARALLELING OF OUTPUTS
any combination of outputs together. R
have an inherent positive temperature coefficient providing
balanced current sharing between outputs without
destructive operation (bipolar outputs could not be paralleled
in this fashion as thermal run-away would likely occur). The
device can even be operated with all outputs tied together.
This mode of operation may be desirable in the event the
application requires lower power dissipation, or the added
capability of switching higher currents.
corresponding decrease in R
Open Load Detect Currents and the Output Current Limits
increase correspondingly (by a factor of eight if all outputs are
paralleled). Less than 125mΩ R
limiting of eight to 24A will result if all outputs are paralleled
The Short Fault Protect Disable (SFPD) pin is used to
The 33298 has extremely low power consumption in both
Using MOSFETs as output switches permits connecting
Performance of parallel operation results in a
MCU
PWR
DD
Reset
by only 20µA per output. Each output
Figure 17. Power ON Reset
≤ 2.0V, the current consumed by the VPWR
Analog Integrated Circuit Device Data
V
DD
RDLY
C
DS(ON)
DLY
DS(ON)
Freescale Semiconductor
while the Output OFF
PWR
DS(ON)
at 25°C with current
current.
33298
+
Reset
of MOSFETs
20µA
DD
= 5.0V