MC10XS3412CPNA Freescale, MC10XS3412CPNA Datasheet - Page 39
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MC10XS3412CPNA
Manufacturer Part Number
MC10XS3412CPNA
Description
Manufacturer
Freescale
Datasheet
1.MC10XS3412CPNA.pdf
(53 pages)
Specifications of MC10XS3412CPNA
Switch Type
High Side
Power Switch Family
MC10XS3412
Input Voltage
4 to 28V
Power Switch On Resistance
36/44Ohm
Output Current
6A
Number Of Outputs
4
Mounting
Surface Mount
Supply Current
6.5mA
Package Type
PQFN
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Pin Count
24
Lead Free Status / RoHS Status
Compliant
mode, as described
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
through the SPI.
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe Mode for V
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
reference by PWM module, as described in the following
Table
feedback on CSNS output pin, as shown in
Table 21. CSNS Reporting Selection
Table 22. Output Current Recopy Selection
Analog Integrated Circuit Device Data
Freescale Semiconductor
TEMP_en
Table 20. PWM Module Selection
CSNS1 (D3)
Table 19. Over-current Mode Selection
PWM_en (D7) CLOCK_sel (D6)
OC_mode_s (D0)
Bit D0 (OC_mode_sel) allows to select the over-current
The GCR register allows the MCU to configure the device
Bit D8 allows the MCU to enable or disable the V
Bit D7 allows the MCU to enable or disable the PWM
Bit D6 (CLOCK_sel) allows to select the clock used as
Bits D5:D4 allow the MCU to select one of two analog
(D5)
X
0
1
0
0
1
20.
0
1
1
0
1
CSNS_en
(D4)
CSNS0 (D2)
0
1
0
0
1
0
Table
current recopy of selected output (D3:2] bits)
only inrush current management (default)
DD
X
0
1
inrush current and bulb cooling
< V
19.
temperature on GND flag
DD(FAIL).
CSNS tri-stated (default)
Over-current Mode
CSNS reporting
management
PWM module enabled with
PWM module enabled with
internal calibrated clock
external clock from IN0
PWM module disabled
CSNS reporting
HS0 (default)
PWM module
HS1
HS2
(default)
Table
21.
DD
failure
(D0). When this bits is [0], the over-voltage is enabled (default
value).
ADDRESS 00111 — CALIBRATION REGISTER
(CALR)
clock, as explained in
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a
word.
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1
and OCR registers.
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
the STATR-selected register data at the time that the
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
Table 22. Output Current Recopy Selection
CS
The GCR register disables the over-voltage protection
The CALR register allows the MCU to calibrate internal
When the
Any bits clocked out of the Serial Output (SO) pin after the
A valid message length is determined following a
SO data will represent information ranging from fault
Note that the SO data will continue to reflect the
The output status register correctly reflects the status of
• The previous SPI communication was determined to be
• The VPWR voltage is below 4.0 V, the status must be
transition, is dependent upon the previously written SPI
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
ignored by the MCU.
1
CS
pin is pulled low, the output register is
1
Figure
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
12.
CS
pin first transitioned to a
HS3
10XS3412
CS
CS
is
39