STPCE1EDBC STMicroelectronics, STPCE1EDBC Datasheet - Page 28
STPCE1EDBC
Manufacturer Part Number
STPCE1EDBC
Description
Manufacturer
STMicroelectronics
Datasheet
1.STPCE1EDBC.pdf
(87 pages)
Specifications of STPCE1EDBC
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Processing Unit
Microprocessor
Operating Supply Voltage (min)
2.45/3V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.7/3.6V
Package Type
BGA
Screening Level
Commercial
Pin Count
388
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Supplier Unconfirmed
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STRAP OPTION
3.1. POWER ON STRAP REGISTER DESCRIPTIONS
3.1.1. STRAP REGISTER 0 CONFIGURATION
28/87
Strap0
Bit Number Sampled
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Bit 7
MD7
0
0
1
7
Bits 7-6
Bits 3-2
Bits 1-0
Bit 5
Bit 4
Bit 6
X
MD6
0
1
6
This register defaults to the values sampled on MD[7:0] pins after reset
PCICLK frequency between 16 & 32 MHz
PCICLK frequency between 32 & 64 MHz
Reserved
Description
Mnemonic
MD[7:6]
MD[3:2]
MD5
MD4
Rsv
MD5
5
Table 3-2. PCI Clock Programming
Release 1.3 - January 29, 2002
Access = 0022h/0023h
Description
PCICLK Programming; the PCICLK PLL is setup through
MD[7:6]. The PLL setup will vary depending on the PCICLK
frequency. See
This bit reflects the value sampled on MD[5] pin and controls the MCLK/
HCLK Synchronization. When MCLK and HCLK frequency are the same,
when set to 1 it unifies HCLK and MCLK and so improves system
performance.
This bit reflects the value sampled on MD[4] pin and controls the
PCICLKO division. It works in conjunction with MD[17]; refer to
3.1.3.
See
Reserved.
MD4
4
Section 3.1.4.
bit 1 for more details.
MD3
Table 3-2
3
for details.
MD2
2
1
Regoffset = 04Ah
Rsv
Section
0
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