STPCE1EDBC STMicroelectronics, STPCE1EDBC Datasheet - Page 5

• Manufacturer Part Number: STPCE1EDBC
• Manufacturer: STMicroelectronics

Specifications of STPCE1EDBC

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 2.45/3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.7/3.6V
• Package Type: BGA
• Screening Level: Commercial
• Pin Count: 388
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Supplier Unconfirmed

1. GENERAL DESCRIPTION
At the heart of the STPC Elite is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, a high speed PCI local-bus controller
and Industry standard PC chip set functions
(Interrupt controller, DMA Controller, Interval timer
and ISA bus) and EIDE controller.
The processor bus runs at the speed of the
processor (x1 mode) or half the speed (x2 mode).
The STMicroelectronics x86 processor core is
embedded with standard and application specific
peripheral modules on the same silicon die. The
core has all the functionality of the ST standard
x86 processor products, including the low power
System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While
running in isolated SMM address space, the SMM
interrupt routine can execute without interfering
with
programs.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated with the x86 processor core.
The PCI bus is the main data communication link
to the STPC Elite chip. The STPC Elite translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports generation of
Configuration cycles on the PCI bus. The STPC
Elite, as a PCI bus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PCI devices.
The STPC Elite integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Elite chip set through this bus.
An industry standard EIDE (ATA 2) controller is
built in to the STPC Elite and connected internally
via the PCI bus.
1.1. MEMORY CONTROLLER
The STPC handles the memory data (DATA) bus
directly, controlling from 8 to 128 MBytes. The
SDRAM controller supports accesses to the
Memory Banks to/from the CPU (via the host).
Parity is not supported.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
the
operating
system
or
Release 1.3 - January 29, 2002
application
Table 1-1. Memory configurations
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (see
The SDRAM Controller supports buffered or
unbuffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type
access.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
1.2. POWER MANAGEMENT
The STPC Elite core is compliant with the
Advanced
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit
consumption, providing a comprehensive set of
features that controls the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides the
following hardware structures to assist the
software
consumption:
- System Activity Detection.
Bank size
Memory
16Mx64
32Mx64
16Mx64
32Mx64
1Mx64
2Mx64
4Mx64
4Mx64
8Mx64
4Mx64
8Mx64
(PMU)
in
Power
Number
module
managing
16
16
16
16
4
8
4
8
4
8
8
GENERAL DESCRIPTION
Management
Organisa
2Mx16x2
1Mx16x4
2Mx16x2
4Mx8x2
8Mx4x2
2Mx8x4
4Mx4x4
4Mx8x4
controls
the
1Mx16
2Mx8
4Mx4
tion
system
Table
the
128Mbits
16Mbits
64Mbits
Device
1-1)
Size
(APM)
power
power
5/87