NS7520B-1-C55 Digi International, NS7520B-1-C55 Datasheet - Page 26
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NS7520B-1-C55
Manufacturer Part Number
NS7520B-1-C55
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C55
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
NS7520B-1-C55
Manufacturer:
IR
Quantity:
4 954
Company:
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Manufacturer:
Digi International
Quantity:
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Part Number:
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Manufacturer:
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Many internal NS7520 features are configured when the RESET pin is asserted. The address bus
configures the appropriate control register bits at powerup. This table shows which bits control
which functions:
Table 3: NS7520 test modes
JTAG
The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520 pins can be
controlled using the JTAG interface port. The JTAG interface provides access to the ARM7TDMI
debug module when the appropriate combination of
shown in Table 3: "NS7520 test modes").
ARM Debug
The ARM7TDMI core uses a JTAG TAP controller that shares the pins with the TAP controller used for
1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller,
{PLLTST_,BISTEN_,SCANEN_}
2 2
NS7520 bootstrap initialization
ADDR[27]
ADDR[26]
ADDR[24:23]
ADDR[19:9]
ADDR[8:7]
ADDR[6:5]
ADDR[4:0]
N S 7 5 2 0 b o o t s t r a p i n i t i a l i z a t i o n
Address bit
Endian configuration
CPU bootstrap
CS0/MMCR[19:18] setting
GEN_ID setting
PLL IS setting
PLL FS setting
PLL ND setting
Name
N S 7 5 2 0 D a t a s h e e t
must be set as shown in Table 3: "NS7520 test modes".
0 3 / 2 0 0 6
PLLTST_
0
1
0
1
00
01
10
11
GEN_ID=A[19:09],default=
IS=A[8:7], default=
FS=A[6:5], default=
ND=A[4:0], default=
Description
Little Endian configuration
Big Endian configuration
CPU disabled; GEN_BUSER=1
CPU enabled; GEN_BUSER=0
,
8-bit SRAM, 63 wait-states/b00
32-bit SRAM, 63 wait-states/
32-bit SRAM
16-bit SRAM, 63 wait-states/b11
BISTEN_
, and
’b10
’b00
SCANEN_
’b01011
’h3ff
is selected (as
b
01