MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 178
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MC9S08SH4CTG
Manufacturer Part Number
MC9S08SH4CTG
Description
Manufacturer
Freescale
Datasheet
1.MC9S08SH4CTG.pdf
(338 pages)
Specifications of MC9S08SH4CTG
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
256Byte
# I/os (max)
13
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
4KB
Lead Free Status / RoHS Status
Compliant
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.4.3
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches
the general call address as well as its own slave address. When the IIC responds to a general call, it acts as
a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after
the first byte transfer to determine whether the address matches is its own slave address or a general call.
If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied
from a general call address by not issuing an acknowledgement.
11.5
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You
can determine the interrupt type by reading the status register.
11.6.1
The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion
of byte transfer.
11.6.2
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
11.6.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
178
Resets
Interrupts
General Call Address
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
Match of received calling address
Complete 1-byte transfer
Interrupt Source
Arbitration Lost
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Table 11-12. Interrupt Summary
Status
ARBL
IAAS
TCF
Table 11-12
IICIF
IICIF
IICIF
Flag
Local Enable
occur, provided the IICIE bit
IICIE
IICIE
IICIE
Freescale Semiconductor
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