MCIMX357CJM5B Freescale, MCIMX357CJM5B Datasheet
MCIMX357CJM5B
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MCIMX357CJM5B Summary of contents
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... ARM1136JF-S™ core running at 532 MHz that is boosted by a multi-level cache system and integrated features such as LCD controller, Ethernet, and graphics acceleration for creating rich user interfaces. © Freescale Semiconductor, Inc., 2010. All rights reserved. Document Number: MCIMX35SR2CEC Rev. 8, 04/2010 MCIMX35 Package Information Plastic package Case 5284 mm, 0 ...
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... Asynchronous sample rate converter (ASRC) • 1-Wire • Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s) • Parallel display (primary up to 24-bit, 1024 x 1024) i.MX35 Applications Processors for Industrial and Consumer Products, Rev Freescale Semiconductor ...
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... MCIMX357DJQ5C 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!) 2 Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1. ...
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... AIPS (2) SSI ETM ASRC CAN(2) Internal ATA Memory IIM FEC RTICv3 RNGC SCC KPP PWM OWIRE MMC/SDIO Bluetooth Keypin or WLAN Accelerator HS USBOTG HS USBOTGPHY HS USBHost FS USBPHY GPU 2D eSDHC(3) ECT ECT IOMUX GPIO(3) GPIO(3) EPIT Timers RTC WDOG GPT Connectivity Access Freescale Semiconductor ...
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... The ARM1136JF-S processor core features are as follows: • Integer unit with integral EmbeddedICE • Eight-stage pipeline i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor to the nwells, and one that is lower than V DD ® technology (which enables direct execution of Java ™ ...
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... THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. Integrated Memory Features • 16-Kbyte instruction cache • 16-Kbyte data cache • 128-Kbyte L2 cache • 32-Kbyte ROM • 128-Kbyte RAM Brief Description Freescale Semiconductor ...
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... EPIT(2) Enhanced ARM periodic interrupt timer i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Subsystem Connectivity The ATA block attachment host interface. Its main use is to peripherals interface with IDE hard disk drives and ATAPI optical disk drives. It interfaces with the ATA device over a number of ATA signals ...
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... The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock internal clock. Multimedia This module accelerates OpenVG and GDI graphics. peripherals Note: Brief Description Freescale Semiconductor ...
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... OSC24M OSC24M Analog 24-MHz reference oscillator i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Subsystem 2 ARM1136 Inter-integrated circuit (I platform serial bus that provides a simple, efficient method of data exchange, peripherals minimizing the interconnection between devices. I applications requiring occasional communications over a short distance among many devices ...
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... Connectivity The SSI is a full-duplex serial port that allows the processor peripherals connected communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the I 2 sound (I S) bus standard. The SSIs interface to the AUDMUX for flexible audio routing. ...
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... This section provides the device-level electrical characteristics for the IC. See to the individual tables and sections. Absolute Maximum Ratings i.MX35 Operating Ranges Interface Frequency i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 4. Table 4. Special Function Related Pins Mux Mode ALT0 External clock input for ARM clock ...
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... Min. Typical Max. Units 1.22 — 1.47 V 1.33 — 1. — — V 1.7 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V 1.75 — 3.6 V Freescale Semiconductor ...
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... FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be supplied by following the power up sequence given in 4.1.2 Interface Frequency Limits Table 8 provides information on interface frequency limits. ID Parameter 1 JTAG TCK Frequency i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Symbol NVCC_MISC 2 NVCC_MLB PHY1_VDDA USBPHY1_VDDA_BIAS USBPHY1_UPLLVDD PHY2_VDD OSC24M_VDD OSC_AUDIO_VDD ...
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... Applications Processors for Industrial and Consumer Products, Rev Table 9. i.MX35 Power Modes QVCC (ARM/L2 MVDD/PVDD Peripheral) Typ. Max. Typ. mA — 16 7.2 mA 12.4 mA — 7 — µA 1.1 400 OSC24M_VDD OSC_AUDO_VDD Max. Typ. Max. — mA — 1.2 — 1.2 mA — — mA — 1.2 Freescale Semiconductor ...
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... The power-up sequence should be completed as follows: 1. Assert Power on Reset (POR). 2. Turn on digital logic domain and IO power supply: VDDn, NVCCx 3. Wait until VDDn and NVCCx power supplies are stable + 32 μs. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor QVCC (ARM/L2 MVDD/PVDD Peripheral) Typ. ...
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... The power-up sequence in reverse order is recommended for powering down. However, all power supplies can be shut down at the same time. 4.4 Reset Timing There are two ways of resetting the i.MX35 using external pins: • Power On Reset (using the POR_B pin) i.MX35 Applications Processors for Industrial and Consumer Products, Rev Freescale Semiconductor ...
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... The table shows values representing maximum current numbers for the i.MX35 under worst case voltage and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 17 ...
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... MHz. Common supplies have been bundled according to the i.MX35 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX35 power supply requirements will be satisfied during startup and transient conditions. Freescale recommends that system current measurements be taken with customer-specific use-cases to reflect normal operating conditions in the end system ...
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... Drive Mode Mobile DDR (1.8 V) SDRAM (1.8 V) SDRAM (3.3 V) DDR2 (1.8 V) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 11. Thermal Resistance Data Condition Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — ...
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... NVCC –0.3 V — V — 410 — mV 330 0.5 × NVCC — V 0.5 × NVCC — — V — 22 — kΩ — 47 — kΩ — 100 — kΩ — 100 — kΩ — — 4.8 kΩ — — 5.9 kΩ Freescale Semiconductor ...
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... Low-Level DC CMOS input voltage Differential receiver VTH+ Differential receiver VTH– Input current (no pull-up/down) Tri-state I/O supply current i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Test Condition Voh — Vol — Ioh — Iol — ...
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... V — — 0.4 V –4.0 — — mA –8.0 –12.0 4.0 — — mA 8.0 12.0 2.0 — 3.6 V –0.3V — 0.8 V μA — — ±1 μA — — ±1 Freescale Semiconductor ...
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... Table 15. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode Parameter Duty cycle Output pin slew rate (max. drive) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 80% 20% PA1 through Table 19 are not applicable for the output open drain [NVCC = 3.0 V– ...
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... V/ns 0.85/1.24 1.26/1.70 1.19/1.71 1.78/2.39 V/ns 0.63/0.95 0.95/1.30 0.80/1.19 1.20/1.60 V/ns 0.43/0.64 0.63/0.87 108 250 mA/ns 113 262 82 197 mA/ns 86 207 52 116 mA/ns 55 121 Max. Typ. Units Rise/Fall — 0.72/0.97 1.2/1.5 V/ns 0.43/0.61 0.72/0.95 0.59/0.81 0.98/1.27 V/ns 0.34/0.50 0.56/0.72 Freescale Semiconductor ...
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... Output pin di/dt (high drive) Output pin di/dt (standard drive) Table 19. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode Parameter Duty cycle i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor [NVCC = 1.65 V–1.95 V] (continued) Min. Symbol Test Condition Rise/Fall tps ...
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... Max. Typ. Units Rise/Fall 133 — MHz 1.35/1.5 2.15/2.19 V/ns 0.72/0.81 1.12/1.16 157 373 mA/ns 167 396 Max. Units NVCC + 0.3 V NVCC ÷ 2 – 0.25 V NVCC ÷ 0.125 V Freescale Semiconductor ...
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... Output pin di/dt (standard drive) Table 24. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) Parameter Clock frequency 1 Output pin slew rate (max. drive) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Min. Symbol Test Condition Rise/Fall Fduty — ...
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... Applications Processors for Industrial and Consumer Products, Rev Min. Symbol Test Condition Rise/Fall didt trfi 1.0 pF 0.07/0.08 tpi 1.0 pF 0.35/1.17 tpi 1.0 pF 1.18/1.99 Max. Typ. Units Rise/Fall 202 435 mA/ns 213 456 0.11/0.12 0.16/0.20 ns 0.63/1.53 1.16/2.04 ns 1.45/2.35 1.97/2.85 ns Freescale Semiconductor ...
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... SS n [3:0] lead time (CS setup time) CS6 SS n [3:0] lag time (CS hold time) CS7 MOSI setup time CS8 MOSI hold time CS9 MISO setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor CS2 CS3 CS3 CS2 CS3 CS2 CS3 CS2 Symbol ...
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... Table 27 lists the timing parameters. Min. Max. Units 5 — — ns Unit Comments MHz 1 Fmodulation < 50 kHz 50 kHz < Fmodulation 300 Hz Fmodulation > 300 KHz μs — μs — mV Fmodulation < 50 kHz 50 kHz < Fmodulation 300 Hz Fmodulation > 300 KHz Freescale Semiconductor ...
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... The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Frequency dependent Figure 10. Trace Data Timing Diagram Min ...
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... Figure 12. Address Latch Cycle Timing DIagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev lists the timing parameters. NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF3 NF4 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF4 Freescale Semiconductor ...
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... Figure 14. Read Data Latch Cycle Timing DIagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Data to NF NF14 ...
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... N/A tDHR N/A Table 26, "DPLL Specifications," on page NOTE Example Timing for ≈ NFC Clock 33 MHz Unit Min. Max. 29 — ns 27.5 — — ns 106 — 8400 — ns 44.5 — — — — — ns 30. Freescale Semiconductor ...
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... OE_B WE10 WE12 EBy_B LBA_B WE14 WE16 Output Data Input Data ECB_B DTACK_B i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 30 lists the timing parameters. WEIM Output Timing WE2 WE3 WE1 ... WEIM Input Timing BCLK WE18 WE20 ...
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... Recommended drive strength for all controls, address and BCLK is set to maximum drive. i.MX35 Applications Processors for Industrial and Consumer Products, Rev Parameter 3 3 NOTE 1 Min. Max. Unit 14.5 — — — 3 3 — — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
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... WE8 RW WE14 LBA OE EB[y] DATA Figure 17. Synchronous Memory Timing Diagram for Write Access— WSC = 1, EBWA = 1, EBWN = 1, LBN = 1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 30 for specific control parameter settings. WE5 V1 V1 WE18 WE5 V1 WE7 WE9 ...
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... WE24, WE25 WE22, WE23 WE20, WE21 WE20, WE21 V1 V1+2 Halfword Halfword WE18, WE19 WSC = 2, SYNC = 1, DOL = 0 Address V1 WE15 WE24, WE25 WE22, WE23 WE17 WE17 V1 V1+4 V1+8 WE16 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword WE5 WE7 WE9 WE13 V1+12 Freescale Semiconductor ...
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... RW LBA OE WE12 EB[y] Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor WE5 Address V1 WE16 Write WE15 WSC = 7, LBA = 1, LBN = 1, LAH = 1 WE5 Address V1 ...
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... Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5) i.MX35 Applications Processors for Industrial and Consumer Products, Rev Table 31 help to determine timing parameters relative chip select (CS) WE32 Address V1 WE40 WE36 WE38 V1 WE43 MAXDI WE31 D(V1) Addr. V1 WE32A WE40 WE39 WE37 Next Address WE44 WE44 WE36 WE38 Freescale Semiconductor ...
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... BE[y] DATA Figure 24. Asynchronous Memory Write Access CS[x] ADDR/ M_DATA RW LBA OE BE[y] Figure 25. Asynchronous A/D Mux Write Access i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr. V1 WE32A ...
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... CSA) ns — 3 – (WEN_CSN) ns — (OEA – CSA (OEA + RLBN + ns RLBA + ADH + 1 – CSA) — 3 – (OEN – CSN — (RBEA – CSA — 3 – (RBEN – CSN) ns — (LBA – CSA) ns — 3 – CSN ns Freescale Semiconductor ...
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... DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Determination By Synchronous Measured ...
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... SD4 SD5 COL/BA SD8 SD10 SD9 Data SD4 Note: CKE is high during the read/write cycle. SD5 Parameter Symbol Min. Max. Unit tCH 3.4 4.1 ns tCL 3.4 4.1 ns tCK 7.0 — ns tCMS 2.0 — ns tCMH 1.8 — ns tAS 2.0 — ns Freescale Semiconductor ...
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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 32 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Parameter NOTE indicates SDRAM requirements. All output signals Symbol Min. ...
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... SD4 SD5 SD4 SD5 SD5 COL/BA SD14 DATA Symbol Min. Max. Unit tCH 0.45 0.55 ns tCL 0.45 0.55 ns tCK 7.0 — ns tCMS 2.4 — ns tCMH 1.4 — ns tAS 2.4 — ns tAH 1.4 — ns tDS 2.4 — ns tDH 1.4 — ns Freescale Semiconductor ...
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... Parameter SD1 SDRAM clock high-level width SD2 SDRAM clock low-level width SD3 SDRAM clock cycle time SD6 Address setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor NOTE SD1 SD2 SD3 SD10 SD10 ROW/BA Symbol Min. tCH 3 ...
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... SDCLK CS RAS CAS WE ADDR BA SD16 CKE Don’t care Figure 30. SDRAM Self-Refresh Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Symbol tAH tRP 1 tRC NOTE SD16 Min. Max. Unit 1.8 — clock 2 20 clock Freescale Semiconductor ...
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... DDR1 SDRAM clock high-level width DDR2 SDRAM clock low-level width DDR3 SDRAM clock cycle time DDR4 CS, RAS, CAS, CKE, WE setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor NOTE Symbol tCKS DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 ...
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... SDCLK_B differential slew rate of 2 V/ns. For different values, use the derating table. Table 37. Derating Values for DDR2–400, DDR2–533 i.MX35 Applications Processors for Industrial and Consumer Products, Rev DDR2-400 Symbol Min 1 t 0.475 0. 0.475 IH NOTE Unit Max — ns — ns — ns Freescale Semiconductor ...
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... DDR23 DQS low level width These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of 1 V/ns. For different values use the derating table. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor DDR22 DDR23 DDR18 ...
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... DQS (input) DDR24 DQ (input) Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Table 38. DDR Single-ended Slew Rate NOTE DDR25 DATA DATA DATA DATA DATA DATA DATA DATA Freescale Semiconductor ...
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... Write cycle DQS falling edge to SDCLK output delay time. SD20 Write cycle DQS falling edge to SDCLK output hold time. 1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Symbol t DQSQ 1 t ...
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... Applications Processors for Industrial and Consumer Products, Rev NOTE SD22 SD21 Data Data Data Data Data Parameter NOTE Data Data Data Symbol Min. Max. Unit tDQSQ — 0.85 ns tQH 2.3 — ns tDQSCK — 6.7 ns Freescale Semiconductor ...
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... FSR input (wl) high before SCKR falling edge 75 FSR input hold time after SCKR falling edge 78 SCKT rising edge to FST out (bl) high 79 SCKT rising edge to FST out (bl) low i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 1,2 Symbol Expression 4 × SSICC 4 × × ...
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... Min. Max. Condition Unit — 20 — 10 — 22 — 12 — 19 — 9 — 20 — 10 — 22 — 17 — 18 — 13 — 21 — 16 2.0 — 18.0 — 2.0 — 18.0 — 4.0 — 5.0 — Freescale Semiconductor ...
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... SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out 89 FST (Bit) In FST (Word) In i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor First Bit Figure 37. ESAI Transmitter Timing 83 87 Last Bit 57 ...
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... HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO can reach 50 MHz. i.MX35 Applications Processors for Industrial and Consumer Products, Rev First Bit Last Bit 75 74 Figure 38. ESAI Receiver Timing Table 43 lists the eSDHCv2 timing characteristics. The Table 43 Freescale Semiconductor ...
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... In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor SD4 SD2 SD1 SD5 ...
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... FEC_RX_ER Figure 40. MII Receive Signal Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Table 44 lists MII receive channel timings. Table 44. MII Receive Signal Timing 1 Table 44 Min. Max. Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period M4 Freescale Semiconductor ...
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... Characteristic 1 M9 FEC_CRS to FEC_COL minimum pulse width 1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 45 lists MII transmit channel timings. Table 45. MII Transmit Signal Timing 1 Min. 5 — ...
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... M15 FEC_MDC pulse width low i.MX35 Applications Processors for Industrial and Consumer Products, Rev Table 46. M9 Table 47 Table 47. MII Transmit Signal Timing lists MII serial management Min. Max. Units 0 — ns — — — ns 40% 60% FEC_MDC period 40% 60% FEC_MDC period Freescale Semiconductor ...
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... I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table M14 M10 ...
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... C-bus Freescale Semiconductor ...
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... LZ0P3714 (CCD) Motorola MC30300 (Python) National Semiconductor LM9618 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors have not been validated at the time of publication. 4.9.12.2 Functional Description There are three timing modes supported by the IPU. ...
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... Figure 46. Non-Gated Clock Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Active Line n+1th frame invalid 1st byte Section 4.9.12.2.2, “Gated Clock Figure n+1th frame invalid 1st byte 1st byte Mode”), 46. All incoming pixel clocks are 1st byte Freescale Semiconductor ...
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... Section 4.9.13.4, “Asynchronous Interfaces” • Section 4.9.13.5, “Serial Interfaces, Functional Description” i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor is that of a Motorola sensor. Some other sensors may have slightly Table 50 lists the timing parameters. 1/IP1 ...
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... All figure parameters shown are programmable. The timing images correspond to inverse polarity i.MX35 Applications Processors for Industrial and Consumer Products, Rev LINE 2 LINE 3 LINE LINE n – 1 LINE n m – Freescale Semiconductor ...
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... Table 51. Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter IP5 Display interface clock period IP6 Display pixel clock period IP7 Screen width IP8 HSYNC width i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor IP7 IP6 IP9 Start of frame IP14 IP12 Figure 49 and Figure Symbol 1 ...
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... Tsw Tsh Tvsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH + 1) × Tdpcp else (V_SYNC_WIDTH + 1) × Tsw BGYP × Tsw Tvbi1 (SCREEN_HEIGHT – BGYP – FH) × Tsw Tvbi2 DISP3_IF_CLK_PER_WR ⋅ HSP_CLK ----------------------------------------------------------------- - HSP_CLK_PERIOD IP20 IP18 IP17 IP19 Value Units Table 52 lists the timing Freescale Semiconductor ...
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... Sharp HR-TFT panel interface timing, and CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Symbol Min. 2 Tckl Tdicd – ...
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... Horizontal timing D1 D2 D320 IP21 1 DISPB_D3_CLK period IP23 IP25 IP26 Symbol (BGXP – 1) × Tdpcp Tsplr CLS_RISE_DELAY × Tdpcp Tclsr CLS_FALL_DELAY × Tdpcp Tclsf PS_FALL_DELAY × Tdpcp Tpsf PS_RISE_DELAY × Tdpcp Tpsr REV_TOGGLE_DELAY × Tdpcp Trev The timing Value Units Freescale Semiconductor ...
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... At a transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Section 4.9.13.1.5, “Interface to Active Matrix Figure 53 depicts the 73 ...
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... Line and Field Timing - NTSC 623 624 625 1 2 Odd Field 310 311 312 313 314 Line and Field Timing - PAL Odd Field 268 269 273 Even Field 315 316 336 Even Field Freescale Semiconductor ...
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... ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_Dn_CS, DISPB_Dn_WR and DISPB_Dn_RD signals. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Figure 54, 75 ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
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... DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 77 ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
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... Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 79 ...
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... Applications Processors for Industrial and Consumer Products, Rev Figure 58 shows the timing of the parallel interface with WRITE OPERATION DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 Figure 62 depict timing of asynchronous parallel interfaces based on Table 54 lists the timing parameters at display access level. All READ OPERATION Freescale Semiconductor ...
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... IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor IP28, IP27 IP31, IP29 read point Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 ...
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... IP46,IP44 Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev IP28, IP27 IP31, IP29 read point IP38 Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 IP32, IP30 IP40 Freescale Semiconductor ...
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... IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor IP28, IP27 IP31, IP29 read point IP38 Read Data IP39 IP47 IP45, IP43 IP42, IP41 ...
Page 84
... Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr IP36, IP34 IP32, IP30 IP38 IP40 1 Max. Units 2 Tdicpr + 1.5 3 Tdicpw + 1 – Tdicur Tdicdr – Tdicur + 1.5 Tdicpr – Tdicdr + Tdicur + 1.5 6 – Tdicdw – Tdicuw + 1.5 7 Tdicpw – Tdicdw + Tdicuw + 1.5 — — Freescale Semiconductor ...
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... T cei l --------------------------------------------------------------------- - HSP_CLK 2 HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Min. Typ. Tdicuw – 1.5 Tdicuw Tdicpw – Tdicdw 0 Tdrp – Tlbd – Tdicdr + 1.5 Tds Tdicdw – ...
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... The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word whole burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers ( 2). i.MX35 Applications Processors for Industrial and Consumer Products, Rev Freescale Semiconductor ...
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... DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) Figure 64. 4-Wire Serial Interface Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Input or output data Write Output data ...
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... DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS Figure 65. 5-Wire Serial Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Write Preamble Read RW Preamble display IF clock cycle Output data 1 display IF clock cycle Input data Freescale Semiconductor ...
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... DISPB_SER_RS clock cycle 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_SER_RS clock cycle Figure 66. 5-Wire Serial Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Write Preamble Read RW Preamble display IF clock cycle ...
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... Tdicuw Tdicur – 1.5 Tdicur IP57, IP55 IP51, IP53 IP59 IP61 1 Max. Units Tdicpr + 1.5 3 Tdicpw + 1.5 5 – Tdicur Tdicdr – Tdicur + 1.5 Tdicpr – Tdicdr + Tdicur + 1.5 6 – Tdicdw – Tdicuw + 1.5 7 Tdicpw – Tdicdw + Tdicuw + 1.5 — Freescale Semiconductor ...
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... --------------------------------------------------------------------- - HSP_CLK 2 HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 1 Min. Typ. Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr Tdicuw – 1.5 Tdicuw Tdicpw – Tdicdw 0 — ...
Page 92
... Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 parameters. MSHC_SCLK tSCLKr Figure 68. MSHC_CLK Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev depict the MSHC timings, and Table 56 tSCLKc tSCLKwh tSCLKwl tSCLKf and Table 57 list the timing Freescale Semiconductor ...
Page 93
... MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Intput) Figure 69. Transfer Operation Timing Diagram (Serial) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor tSCLKc tBSsu tDsu tDd tBSh tDh 93 ...
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... NOTE Parameter Symbol Cycle tSCLKc H pulse length tSCLKwh L pulse length tSCLKwl Rise time tSCLKr Fall time tSCLKf Setup time tBSsu Hold time tBSh tBSh tDh 1 Standards Unit Min. Max. 50 — — — ns — — — — ns Freescale Semiconductor ...
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... Table 58. MLB 256/512 Fs Timing Parameters Parameter Symbol 1 MLBCLK operating frequency f mck MLBCLK rise time t mckr i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Parameter Symbol Setup time tDsu Hold time tDh Output delay time tDd Symbol tSCLKc tSCLKwh ...
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... Fs PLL unlocked 512 × 512 × Fs PLL unlocked Note ns — ns — ns — Note Comment Min: 1024 × 44.0 kHz Typ: 1024 × 48.0 kHz Max: 1024 × 48.1 kHz Max: 1024 × Fs PLL unlocked — ns PLL unlocked Freescale Semiconductor ...
Page 97
... Table 60. RPP Sequence Delay Comparisons Timing Parameters ID Parameters OW1 Reset time low OW2 Presence detect high OW3 Presence detect low OW4 Reset time high i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Min Typ Max Units 9.7 10.6 — 9.3 10.2 — — ...
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... OW8 OW7 OW8 OW7 OW9 Table 62. WR1/RD Timing Parameters Symbol Min. t LOW1 t SLOT t RELEASE Typ. Max. Units 60 100 120 µs 117 120 µs Table 62 lists Typ. Max. Units µs 60 117 120 µs 15 — 45 µs Freescale Semiconductor ...
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... When ata_buffer_en is asserted, the bus should drive from host to device. When ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention on the host and device tri-state buses is always avoided. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Parameter 1 1 ...
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... Table 64. ATA Timing Parameters Description UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ 1 Contributing Factor Peripheral clock frequency 15 ns UDMA0 10 ns UDMA1 7 ns UDMA2, UDMA3 5 ns UDMA4 4 ns UDMA5 5.0 ns 4.6 ns UDMA5 12.0 ns 8.5 ns 8 Transceiver Transceiver Transceiver Cable Cable Cable Cable Cable Freescale Semiconductor ...
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... T > tsu + thi + tskew3 + tskew4 t0 (min.) = (time_1 + time_2 + time_9) × — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 65 lists the timing parameters for PIO read. Figure 76. PIO Read Timing Diagram Table 65. PIO Read Timing Parameters ...
Page 102
... Applications Processors for Industrial and Consumer Products, Rev. 8 102 Table 66 lists the timing parameters for PIO write. Figure 77. PIO Write Timing Diagram Table 66. PIO Write Timing Parameters Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Freescale Semiconductor ...
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... T – (tskew1 + tskew2 + tskew6) tf(write) — tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2) tL — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Figure 79 shows timing for MDMA write. Value Table 67 lists the Controlling ...
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... Figure 80. UDMA-In Transfer Starts Timing Diagram Figure 81. UDMA-In Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 104 Value Figure 81 shows timing when the UDMA-in device terminates transfer, and Controlling Variable time_jn — shows timing when the UDMA-in Freescale Semiconductor ...
Page 105
... There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff large enough to avoid bus contention. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Description Controlling Variable time_ack ...
Page 106
... UDMA-out burst. Figure 83. UDMA-Out Transfer Starts Timing Diagram Figure 84. UDMA-Out Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 106 Figure 84 shows timing when the UDMA-out device terminates transfer, and shows timing when the UDMA-out Freescale Semiconductor ...
Page 107
... T) – (tskew1 + tskew2) tcvh tcvh ton = time_on × T – tskew1 — ton toff = time_off × T – tskew1 toff i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Value Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc — ...
Page 108
... The output is available at the pulse-width modulator output (PWMO) external i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 108 Signal Description US16 US16 US17 US17 Min. Max. — 6.0 — 0.0 — 9.0 Conditions / Unit Reference Signal Freescale Semiconductor ...
Page 109
... VIL Data Inputs Data Outputs Data Outputs Data Outputs Figure 88. Boundary Scan (JTAG) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Figure 87 Figure 89 Table 72 lists the SJC timing parameters. SJ1 SJ2 SJ2 VM VM VIL SJ3 ...
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... Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid Figure 90. TRST Timing Diagram Table 72. SJC Timing Parameters Parameter VIH SJ9 All Frequencies Unit Min. Max. 1 100 — — ns — — — ns — — — — ns — Freescale Semiconductor ...
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... Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Parameter Table 73. SPDIF Timing Parameters Symbol — — — — ...
Page 112
... For internal frame sync operations using the external clock, the FS timing will be the same as that of Tx Data (for example, during AC97 mode of operation). i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 112 srckp srckpl srckph Figure 91. SRCK Timing stclkp stclkpl stclkph Figure 92. STCLK Timing NOTE Freescale Semiconductor ...
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... DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 93. SSI Transmitter with Internal Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 74 SS1 SS3 SS5 SS4 SS8 SS10 SS14 SS15 ...
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... Internal Clock Operation Synchronous Internal Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — — — 15.0 ns — 15.0 ns — 15.0 ns — 10.0 — — ns — Freescale Semiconductor ...
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... DAM1_T_FS (wl) (Output) DAM1_RXD (Input) SS48 DAM1_R_CLK (Output) Figure 94. SSI Receiver with Internal Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 75 lists the timing parameters shown SS1 SS5 SS4 SS9 SS11 SS20 SS21 SS51 ...
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... Applications Processors for Industrial and Consumer Products, Rev. 8 116 Parameter Internal Clock Operation Oversampling Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — — ns 15.04 — — ns — — ns — Freescale Semiconductor ...
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... DAM1_T_FS (wl) (Input) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 95. SSI Transmitter with External Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 76 SS22 SS25 SS26 SS29 SS31 SS37 SS38 SS45 ...
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... External Clock Operation Synchronous External Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
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... Table 77. SSI Receiver with External Clock Timing Parameters ID SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period SS24 (Tx/Rx) CK clock rise time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 77 SS22 SS26 SS25 SS30 SS32 SS35 SS41 ...
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... Bit 4 Bit 5 Bit 6 Min. Max. Unit 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 6.0 ns — 6.0 ns 10.0 — ns 2.0 — ns Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA1 UA1 Freescale Semiconductor ...
Page 121
... UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. the transmit timing characteristics. UA3 TXD (output) Start Bit 0 Bit 1 Bit Figure 99. UART IrDA Mode Transmit Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Symbol Min. t 1/F Tbit baud_rate T ref_clk UA2 Bit 2 ...
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... But accumulation tolerance in one frame must not baud_rate Max. Units 1 – 1 — baud_rate ref_clk 2 (3/16) × (1 — baud_rate baud_rate + T ref_clk Table 81 lists UA5 UA5 STOP Possible Bit 6 Bit 7 BIT Parity Bit Max. Units 2 – 1/F + — baud_rate 1/(16 × baud_rate (5/16) × (1/F ) — baud_rate Freescale Semiconductor ...
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... Receive USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 102. USB Receive Waveform in DAT_SE0 Bidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Figure 101 Signal Description Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low ...
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... Transmit enable, active low Tx data when USB_TXOE_B is low SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Differential Rx data when USB_TXOE_B is high US9 Conditions/Reference Signal — and Figure 104 show the US11 US10 Freescale Semiconductor ...
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... Table 86. Signal Definitions—VP_VM Bidirectional Mode Name Direction USB_TXOE_B Out USB_DAT_VP Out (Tx) In (Rx) USB_SE0_VM Out (Tx) In (Rx) USB_RCV In i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor US15/US17 Signal Min. Max. Source Out — 5.0 Out — 5.0 Out — ...
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... US26 US28 US29 Signal Name Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — USB_TXOE_B Out — USB_DAT_VP Out 49.0 USB_SE0_VM Out –3.0 USB_DAT_VP In — USB_SE0_VM In — US19 US27 Condition/ Max. Unit Reference Signal 51.0 % — +3.0 ns USB_DAT_VP 3 3 Freescale Semiconductor ...
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... In USB_VM1 In USB_RCV In Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US33 Figure 107. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Signal Name Direction Min. USB_DAT_VP In –4.0 USB_RCV In –6.0 Figure 107 Signal Description Transmit enable, active low ...
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... US38 US40 US39 US41 Signal Direction Min. Max. Out — 5.0 Out — 5.0 Out — 5.0 Out 49.0 51.0 Out –3.0 +3.0 In — 3.0 In — 3.0 In –4.0 +4.0 In –6.0 +2.0 Unit Conditions/Reference Signal — ns USB_DAT_VP USB_VM1 ns USB_VP1 Freescale Semiconductor ...
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... Package Information and Pinout This section includes the following: • Mechanical package drawing • Pin/contact assignment information i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 129 ...
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... MAPBGA Production Package 1568-01, 17x17 mm, 0.8 Pitch See Figure 109 for the package drawing and dimensions of the production package. Figure 109. Production Package: Mechanical Drawing i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 130 Freescale Semiconductor ...
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... ATA_BUFF_EN ATA_CS0 ATA_CS1 ATA_DA0 ATA_DA1 ATA_DA2 ATA_DATA0 ATA_DATA1 ATA_DATA10 ATA_DATA11 ATA_DATA12 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor show the signal assignment on the i.MX35 ball map for silicon Ball Location Signal ID A5 ATA_DATA7 D7 ATA_DATA8 F15 ATA_DATA9 D5 ATA_DIOR ...
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... LD17 V8 LD18 W20 LD19 T20 LD2 P3 LD20 N5 LD21 R1 LD22 Ball Location T14 P13 M11 T11 Y11 U11 V11 K2 J5 M20 N17 L3 M1 D20 F20 G18 H20 J18 J16 J19 J17 J20 K14 K19 K18 K20 G17 K16 K17 K15 Freescale Semiconductor ...
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... NGND_EMI1 NGND_EMI2 NGND_EMI3 NGND_EMI3 NGND_JTAG NGND_LCDC NGND_LCDC NGND_MISC NGND_MISC NGND_MLB NGND_NFC NGND_SDIO NVCC_ATA NVCC_ATA NVCC_ATA NVCC_ATA NVCC_CRM NVCC_CSI i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Ball Location Signal ID P1 LD23 P2 LD3 N2 LD4 M3 LD5 N1 LD6 R2 LD7 T2 LD8 N3 LD9 ...
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... TX5_RX0 A9 TXD1 C9 TXD2 B9 USBOTG_OC A8 USBOTG_PWR B8 USBPHY1_DM C8 USBPHY1_DP C16 USBPHY1_RREF A7 USBPHY1_UID B7 USBPHY1_UPLLGND A18 USBPHY1_UPLLVDD C15 USBPHY1_UPLLVDD Ball Location C17 A19 E12 E13 B17 A13 A10 C7 G15 U17 R17 P15 R15 Y7 R16 T16 M16 N19 P19 R19 N18 N14 N15 P17 Freescale Semiconductor ...
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... VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Ball Location Signal ID A17 USBPHY1_VBUS B16 USBPHY1_VDDA_BIAS C14 USBPHY1_VSSA_BIAS A16 USBPHY2_DM A6 USBPHY2_DP B6 VDD D18 VDD ...
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... CSI_MCLK U3 CSI_PIXCLK W2 CSI_VSYNC W1 CSPI1_MISO T4 CSPI1_MOSI V5 CSPI1_SCLK U5 CSPI1_SPI_RDY Y4 CSPI1_SS0 W4 CSPI1_SS1 V4 CTS1 Ball Location E14 W10 U9 V12 E16 Y10 T10 V10 T12 L16 F17 E19 B20 C19 E18 F19 V16 T15 W16 V15 U14 Y16 U15 W17 V14 W15 Y15 T14 Freescale Semiconductor ...
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... DQM3 EB0 EB1 ECB EXT_ARMCLK EXTAL_AUDIO EXTAL24M FEC_COL FEC_CRS FEC_MDC FEC_MDIO FEC_RDATA0 FEC_RDATA1 FEC_RDATA2 FEC_RDATA3 FEC_RX_CLK FEC_RX_DV FEC_RX_ERR i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Ball Location Signal ID G5 FEC_TDATA0 A2 FEC_TDATA1 D4 FEC_TDATA2 D2 FEC_TDATA3 E6 FEC_TX_CLK E3 FEC_TX_EN F5 FEC_TX_ERR D1 FSR ...
Page 138
... SCKT F11 DQM1 G11 SD1 Ball Location G12 F13 F14 G14 P16 H14 J14 L14 M14 R10 P14 E20 V20 U19 T19 T18 M12 M15 N20 N16 P20 R13 P12 W11 Y9 N13 E15 U10 U18 U1 G1 C20 C17 A19 Freescale Semiconductor ...
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... SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 SDBA0 SDBA1 SDCKE0 CAS i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Ball Location Signal ID V18 SDCLK Y19 SDCLK_B R14 SD0 U16 SD15 W18 SD23 V17 A23 A15 ...
Page 140
... VSS N7 VSS R7 VSS F8 VSS R8 VSS F9 VSS F12 NVCC_EMI2 R12 VSS G13 VSS H15 VSS J15 VSS A1 VSS Y1 VSS J8 VSTBY M8 WDOG_RST N8 XTAL_AUDIO J9 XTAL24M Ball Location L9 N9 K10 P10 H11 H12 H13 J13 K13 L13 T17 A20 Y20 T9 Y12 V19 U20 Freescale Semiconductor ...
Page 141
... BUF RES EN _DV RQ 15 F_E ET_ RTS RXD ATA_ ATA_ ATA_ ATA_ 1 1 DATA DATA DATA IOR i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor SD3 SD2 SD2 SDQ SD2 SD1 SDQ SD3 SD2 SD2 SD2 SD2 SD1 ...
Page 142
... USB USB PHY I2C1 USB USB PHY PHY PHY 1_VS _DAT PHY PHY 1_VD 1_UP 1_UP SA 1_UI 1_D DA LLG LLVD NVC TDI NVC USB USB USB PHY C_S C_JT PHY PHY PHY 1_VS DIO AG 1_UP 1_VB 1_DP SA LLVD US D Freescale Semiconductor ...
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... DATA DATA DIOR Product Documentation All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx. 7 Revision History Table 94 shows the revision history of this document. Table 94. i.MX35 Data Sheet Revision History Revision Date Number 8 04/2010 • Updated Table 7 12/18/2009 • Updated ...
Page 144
... Figure 38, “ESAI Receiver Timing,” Figure 37, “ESAI Transmitter Timing.” reverse positions of steps Table 1, “Ordering Information”: PCIMX357CVM5B, Section 4.3.1, “Powering Up.” Table 9, “i.MX35 Power Modes.” modified Figure 16, “Synchronous Figure 21, “Muxed A/D Mode Timing modified to remove extraneous 5 and 6. Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 145 ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 146 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 147 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...