SAA7706H/N107 NXP Semiconductors, SAA7706H/N107 Datasheet - Page 28

• Manufacturer Part Number: SAA7706H/N107
• Manufacturer: NXP Semiconductors

Specifications of SAA7706H/N107

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
The quadrature mixer converts the RDS band to the
frequency spectrum around 0 Hz and contains the
appropriate Q/I signal filters. The final decoder with
CORDIC recovers the clock and data signals. These
signals are output on pins RDS_CLOCK and RDS_DATA.
In the event of FM-stereo reception the clock of the total
chip is locked to the stereo pilot (19 kHz multiple). In the
event of FM-mono the DCS loop keeps the DCS clock
around the same 19 kHz multiple. In all other cases like
AM reception or tape, the DCS circuit has to be set in a
preset position by means of an I
conditions the RDS system is always clocked by the DCS
clock in a 38 kHz (4
2001 Mar 05
handbook, full pagewidth
Car radio Digital Signal Processor (DSP)
(dB)
10
20
30
40
50
60
70
10
0
50
9.5 kHz) based sequence.
52
Fig.17 Detailed frequency response curve RDS channel.
2
C-bus bit. Under these
54
56
28
8.15.2
The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions the data will
remain valid for 400 s after the clock transition. The
timing of the data change is 100 s before a positive clock
change. This timing is suited for positive as well as
negative triggered interrupts on a microcontroller. The
RDS timing is shown in Fig.18. During poor reception it is
possible that faults in phase occur, then the duty cycle of
the clock and data signals will vary from minimum
0.5 times to a maximum of 1.5 times the standard clock
periods. Normally, faults in phase do not occur on a cyclic
basis.
58
T
IMING OF CLOCK AND DATA SIGNALS
60
62
Product specification
SAA7706H
f (kHz)
MGT472
64