ATSAM3303 Atmel, ATSAM3303 Datasheet
ATSAM3303
Specifications of ATSAM3303
Related parts for ATSAM3303
ATSAM3303 Summary of contents
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... Typical Applications: MP3 Player, Musical Instruments, Consumer Electronic, Effect Devices 1. Description The ATSAM3303 is a member of the new ATSAM3000 family that uses the DSP array technology. The ATSAM3303 includes three 24-bit DSPs, a 24-bit Audio Router and a general-purpose 16-bit on-chip CISC microcontroller. Its high performance and flexi- bility allow implementation of professional-quality audio applications, such as MP3 decoding, Wavetable synthesis, effect processing and mixing ...
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... Functional Description 3.1 DSP Array The ATSAM3303 includes three on-chip DSPs. Each DSP (P24) is built around RAM and ROM. The RAM contains both data and P24 instructions; the ROM contains typical coefficients such as FFT cosines and win- dowing. A P24 sends and receives audio samples through the Sync Bus. It can request external data such as compressed audio through the Async Bus ...
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... MMU (Memory Management Unit) The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3303 includes an on-chip 16K x 24 RAM. 3.6 Router: Final ACC, MIX, Audio Out, Audio In This block includes a RAM, accessed through the Async Bus, which defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send) ...
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... Asynchronous serial (MIDI) – Synchronous serial (SPI) Ultra Low-cost Musical Keyboard Switches, ATSAM3303 LCD Display MIDI ROM Stereo Audio DAC Out Keyboard ...
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... Stereo 31-band equalizer @48 kHz The ATSAM3303 runs firmware directly from an external ROM/Flash memory. It may also run firmware from local RAM, thus freeing many I/O pins, which can then be used for application- dependent functions. The ATSAM3303 is the ideal choice when wavetable synthesis or many I/O pins are required ...
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... SCLK 98 CS 100 P0.11 100 SYNC 100 WR 1 SMC 1 P0.12 1 ATSAM3303 6 Type Sharing Description PWR - Digital ground. All these pins should be returned to a ground plane Core power. All these pins should be returned to nominal 1. PWR - PWROUT if the built-in power switch is used. PWR - Periphery power. All these pins should be returned to nominal 3.3V. Power switch input ...
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... Pd DAAD3 - 1 have built-in pull-downs. They may be left open if not used. External DAC/Codec Mute. Sensed at power up. If found high, then I/O 10 MUTE becomes an active high output. If found low, then MUTE becomes an active low output. I/O 10 General-purpose I/O pin ATSAM3303 7 ...
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... WCS0 4 P1.9 4 WOE 48 P1.8 48 WWE 49 P1.7 49 DFCS 23 DFSI 25 DFSO 32 ATSAM3303 8 Type Sharing Description Out 11 External memory address bit, extension to 64 Mbits Out 11 SmartMedia chip enable (CE), active low I/O 11 General-purpose I/O pin Out 12 External memory address bit, extension to 32 Mbits Out 12 SmartMedia address latch enable (ALE) ...
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... In - when power switch is used). To exit from power down, PDWN has to be set high then RESET applied. Alternate programmable power-downs are available which allow warm restart of the chip Test input. Should be grounded or left open. Pd ATSAM3303 ) can be connected to X1 using AC coupling PP 9 ...
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... Pinout by Pin Number Table 6-2. ATSAM3303 Pinout by Pin Number Pin # Pin Name 1 WR SMC P0. R|B P0.13 3 WCS1 P1.10 4 WCS0 P1.9 5 CKOUT 6 CLBD 7 WSBD 8 IRQ INT SMRE FS0 P0.8 9 GND 10 WA0 P2.0 11 WA1 P2.1 12 WA2 P2.2 13 VC3 14 WA3 P2.3 15 WA4 P2.4 16 WA5 P2 ...
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... Figure 7-1. Thin Plastic 100-lead Quad Flat Pack (LQFP100) Table 7-1. Denomination 6091C–DRMSD–21-Apr-06 Package Dimensions in mm Min 1.40 0.05 1.35 0.45 0.13 ATSAM3303 Nom Max 1.50 1.60 0.10 0.15 1.40 1.45 0.60 0.75 14.00 12.00 14.00 12.00 0.40 0.18 0.23 11 ...
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... A Note: 1. Operation at lower V values down to V C33 case of use of these circuits with V ATSAM3303 12 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the + 0 ...
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... MHz, all P24s stopped, warm CC3 start power-down active) V deep power down supply current C18 I CC4 (using power switch) PU/PD Built-in pull-up/pull-down resistor 6091C–DRMSD–21-Apr-06 = 25° 1.8V ± 10 C18 C33 =- ATSAM3303 = 3.3V ± 10%) Min Typ Max -0.3 - 1.0 2 0.3 C33 1 0.3 C18 - - 0.4 2 ...
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... Timings Figure 9-1. Figure 9-2. Table 9-1. Symbol t AVCS t CSLRDL t RDHCSH t PRD t RDLDV t DRH t CSLRWRL t WRHCSH ATSAM3303 14 Host Interface Read Cycle A0 t AVCS CS t CSLRDL Host Interface Write Cycle A0 t AVCS CS t CSLWRL Timing Parameters Parameter Address valid to chip select low ...
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... TE RF Status register is read when • TE: Transmit empty If 0, data from ATSAM3303 to host is pending and IRQ is high. Reading the data will set and clear IRQ. • RF: Receiver full If 0, then ATSAM3303 is ready to accept DATA from host. Note: 9.2 SmartMedia and Other Peripheral Interfaces This is a master 8-bit parallel interface that provides connection to SmartMedia or other peripherals such as LCD screens ...
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... Pins used: CLBD (output), WSBD (output), DABD3 - 0 (outputs), DAAD3 - 0 (inputs) Optionally: CLAD3 - 0 (inputs), WSAD3 - 0 (inputs) The ATSAM3303 allows for 8 digital audio output channels and 8 digital audio input channels. All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived from the IC crystal oscillator. However firmware option, the DAAD3 - 0 inputs can be synchronized with incoming CLAD3 - 0 and WSAD3 - 0 signals ...
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... DABD valid prior/after CLBD rising CLBD cycle time , the crystal period follows: CK Sample Frequency Typical Sample WSBD Frequency 1/(t * 128) 96 kHz CK 1/(t * 192) 64 kHz CK 1/(t * 256) 48 kHz CK 1/(t * 384) 32 kHz CK LSB 16 bits ATSAM3303 t CW CLBD t SOD SOD Min Typ Max CLBD/WSBD t Frequency Ratio C t ...
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... Pins used: WA21 - WA0 (address out), WD15 - WD0 (data bi-directional), WCS0, WCS1 (pre- decodes out), WOE (output enable), WWE (write) When using all address bits, the maximum address range is two pages (WCS0, WCS1 words (total = 16 Mbytes). Figure 9-8. ATSAM3303 18 LSB 16 bits ROM/Flash Read Cycle ...
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... DW t Data out hold time DH 6091C–DRMSD–21-Apr- ns. LCK min. Typical value with crystal 12.288 MHz is 90 ns. ACE External RAM/Flash Write Timing WCS0 WCS1 t CSWE WA0 - WA21 WOE WWE WD0 - WD15 ATSAM3303 Min Typ Max LCK LCK - LCK LCK - LCK - LCK - 5 ...
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... The byte 0ACh is written to the host, this raises IRQ. The host can recognize that the 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3303 firmware. The firmware should begin with string 4. The byte 0ACh is written to the host, this raises IRQ. The host recognizes that the 5 ...
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... Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the ATSAM3303 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM3303. • Buses Parallel layout between and WA0 - WA21/WD0 - WD15 should be avoided ...
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... Recommended Crystal Compensation and LFT Filter Figure 12-1. Recommended Crystal Compensation and LFT Filter ATSAM3303 560 GND X1 X2 LFT 6091C–DRMSD–21-Apr-06 ...
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... A library of frequently used functions is available, such as: • Wavetable synthesis • Reverb/Chorus • MP3 decode • 31-band equalizer • Parametric equalizer Atmel engineers are available to study customer-specific applications. 6091C–DRMSD–21-Apr-06 ® (98, ME, 2000, XP). Within the environment possible to: ATSAM3303 23 ...
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... First issue. 13-Jul-04 Corrected description of RESET pin in 6091B Section 11. ”Recommended Board Layout” on page Changed all references TQFP to LQFP. Changed pin name for Pin No 6091C “ATSAM3303 Pinout by Pin Number,” on page 10 ATSAM3303 24 Table 6-1. Corrected typo in product name in 21. Table 6-2, ...
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