ATSAM3303 Atmel, ATSAM3303 Datasheet - Page 20

• Manufacturer Part Number: ATSAM3303
• Manufacturer: Atmel

Specifications of ATSAM3303

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

10. Reset and Power-down
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ATSAM3303
During power-up, the RESET input should be held low until the crystal oscillator and PLL are
stabilized, which takes max. 10 ms.
After the low-to-high transition of RESET, the following occurs:
The power-up sequence is as follows:
If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is
used, then the chip enters a deep power-down sleep mode, as power is removed from the
core. To exit power down, PDWN has to be asserted high, then RESET applied.
Other power reduction features allowing warm restart are controlled by firmware:
• All P24s enter an idle state.
• P16 program execution starts in built-in ROM.
• STIN is sensed. If HIGH, then the built-in debugger is started.
• Addresses 0 & 1 from external ROM are checked. If “DR” is read, then control is transferred
• SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect
• An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If
• Firmware download from a host processor is assumed.
1. The byte 0ACh is written to the host, this raises IRQ. The host can recognize that the
2. The host sends the firmware size (in words) on two bytes (Low byte first).
3. The host sends the ATSAM3303 firmware. The firmware should begin with string
4. The byte 0ACh is written to the host, this raises IRQ. The host recognizes that the
5. ATSAM3303 starts the firmware.
• P24s can be individually stopped.
• The clock frequency can be internally divided by 256.
to address 400H from external ROM.
(SMPD). When detected, the firmware is downloaded from SmartMedia reserved sector 1
and started.
“DR” is read, then the built-in loader loads the firmware from the external
EEPROM/DataFlash and starts it.
chip is ready to accept program download. Higher speed transfer can be reached by
polling the parallel interface status (CS = 0, A0 = 1, RD = 0).
“DR”.
chip has accepted the firmware.
6091C–DRMSD–21-Apr-06