MCIMX257CJM4A Freescale, MCIMX257CJM4A Datasheet - Page 116

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MCIMX257CJM4A

Manufacturer Part Number
MCIMX257CJM4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX257CJM4A

Lead Free Status / RoHS Status
Compliant

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1
2
3.7.19.1.2
Figure 86
Table 85
1
2
3.7.19.2
The following subsections describe the UART transmit and receive timing in IrDA mode.
3.7.19.2.3
Figure 87
Table 86
116
F
T
Note: The UART receiver can tolerate 1/(16
not exceed 3/(16
F
(output)
ref_clk
baud_rate
baud_rate
UA2
TXD
UA1
(input)
ID
ID
RXD
: The period of UART reference clock ref_clk ( ipg_perclk after RFDIV divider).
describes the timing parameter (UA2) shown in the figure.
describes the timing parameters (UA3–UA4) shown in the figure.
: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16.
: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16.
shows the UART receive timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit.
depicts the UART transmit timing in IrDA mode, showing only 8 data bits and 1 stop bit.
UART Infrared (IrDA) Mode Timing
Start
Bit
UART Receive Timing in RS-232 Serial Mode
UART IrDA Mode Transmit Timing
Transmit Bit Time
Start
UA2
Bit
UA3
Parameter
F
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
baud_rate
Table 84. UART RS-232 Serial Mode Transmit Timing Parameters
Table 85. UART RS-232 Serial Mode Receive Timing Parameters
Figure 86. UART RS-232 Serial Mode Receive Timing Diagram
Bit 0
Receive bit time
Bit 0
Parameter
).
Figure 87. UART IrDA Mode Transmit Timing Diagram
Bit 1
Bit 1
Symbol
1
t
Bit 2
Tbit
F
Bit 2
baud_rate
UA3
UA2
Bit 3
1/F
) tolerance in each bit. But accumulation tolerance in one frame must
Bit 3
baud_rate
Bit 4
Symbol
t
Rbit
Min.
1
Bit 4
Bit 5
– T
1/F
ref_clk
baud_rate
Bit 6
UA4
F
2
Bit 5
baud_rate
Min.
2
Bit 7
– 1/(16
1/F
)
Bit 6
baud_rate
Possible
Par Bit
Parity
UA2
1/F
Bit
Max.
baud_rate
Bit 7
F
+ T
baud_rate
STOP
Max.
Freescale Semiconductor
UA2
BIT
UA3
ref_clk
+ 1/(16
Possible
Parity
)
Bit
Next
Start
Bit
UA3
Units
Units
STOP
BIT

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