CY7C341-25RC Cypress Semiconductor Corp, CY7C341-25RC Datasheet

CY7C341-25RC

Manufacturer Part Number

CY7C341-25RC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C341-25RC.pdf (15 pages)

Specifications of CY7C341-25RC

Family Name

MAX®

# Macrocells

192

Number Of Usable Gates

3750

Frequency (max)

62.5MHz

Propagation Delay Time

25ns

Number Of Logic Blocks/elements

# I/os (max)

Operating Supply Voltage (typ)

In System Programmable

Operating Supply Voltage (min)

4.75V

Operating Supply Voltage (max)

5.25V

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Through Hole

Pin Count

Package Type

Windowed PGA

Memory Type

EPROM

Lead Free Status / RoHS Status

Not Compliant

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BOSTOCK HK LIMITED

Part Number:

CY7C341-25RC

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MOT

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Cypress Semiconductor Corporation

Document #: 38-03034 Rev. *B

Features

Functional Description

The CY7C341 is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX

100% user-configurable, allowing the devices to accom-

modate a variety of independent logic functions.

The 192 macrocells in the CY7C341 are divided into 12 LABs,

16 per LAB. There are 384 expander product terms, 32 per

LAB, to be used and shared by the macrocells within each

LAB. Each LAB is interconnected with a programmable inter-

connect array, allowing all signals to be routed throughout the

chip.

The speed and density of the CY7C341 allows them to be

used in a wide range of applications, from replacement of large

amounts of 7400-series TTL logic, to complex controllers and

multifunction chips. With greater than 37 times the functionality

of 20-pin PLDs, the CY7C341 allows the replacement of over

75 TTL devices. By replacing large amounts of logic, the

CY7C341 reduces board space and part count, and increases

system reliability.

Each LAB contains 16 macrocells. In LABs A, F, G, and L, eight

macrocells are connected to I/O pins and eight are buried,

while for LABs B, C, D, E, H, I, J, and K, four macrocells are

connected to I/O pins and 12 are buried. Moreover, in addition

to the I/O and buried macrocells, there are 32 single product

term logic expanders in each LAB. Their use greatly enhances

the capability of the macrocells without increasing the number

of product terms in each macrocell.

Logic Array Blocks

There are 12 logic array blocks in the CY7C341. Each LAB

consists of a macrocell array containing 16 macrocells, an

expander product term array containing 32 expanders, and an

I/O block. The LAB is fed by the programmable interconnect

array and the dedicated input bus. All macrocell feedbacks go

to the macrocell array, the expander array, and the program-

mable interconnect array. Expanders feed themselves and the

macrocell array. All I/O feedbacks go to the programmable

interconnect array so that they may be accessed by macro-

cells in other LABs as well as the macrocells in the LAB in

which they are situated.

Externally, the CY7C341 provides eight dedicated inputs, one

of which may be used as a system clock. There are 64 I/O pins

• 192 macrocells in 12 logic array blocks (LABs)

• Eight dedicated inputs, 64 bidirectional I/O pins

• 0.8-micron double-metal CMOS EPROM technology

• Programmable interconnect array

• 384 expander product terms

• Available in 84-pin HLCC, PLCC, and PGA packages

•

architecture is

3901 North First Street

USE ULTRA37000™

FOR ALL NEW DESIGNS

that may be individually configured for input, output, or bidirec-

tional data flow.

Programmable Interconnect Array

The Programmable Interconnect Array (PIA) solves inter-

connect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA are the outputs of every

macrocell within the device and the I/O pin feedback of every

pin on the device.

Unlike masked or programmable gate arrays, which induce

variable delay dependent on routing, the PIA has a fixed delay.

This eliminates undesired skews among logic signals, which

may cause glitches in internal or external logic. The fixed

delay, regardless of programmable interconnect array config-

uration, simplifies design by assuring that internal signal

skews or races are avoided. The result is ease of design imple-

mentation, often in a single pass, without the multiple internal

logic placement and routing iterations required for a program-

mable gate array to achieve design timing objectives.

Timing Delays

Timing delays within the CY7C341 may be easily determined

using Warp™, Warp Professional™, or Warp Enterprise™

software. The CY7C341 has fixed internal delays, allowing the

user to determine the worst case timing delays for any design.

Design Recommendations

For proper operation, input and output pins must be

constrained to the range GND < (V

inputs must always be tied to an appropriate logic level (either

connected together directly at the device. Power supply

decoupling capacitors of at least 0.2 µF must be connected

between V

each V

at the device. Decoupling capacitors should have good

frequency response, such as monolithic ceramic types.

Design Security

The CY7C341 contains a programmable design security

feature that controls the access to the data programmed into

the device. If this programmable feature is used, a proprietary

design implemented in the device cannot be copied or

retrieved. This enables a high level of design control to be

obtained since programmed data within EPROM cells is

invisible. The bit that controls this function, along with all other

program data, may be reset simply by erasing the device. The

CY7C341 is fully functionally tested and guaranteed through

complete testing of each programmable EPROM bit and all internal

logic elements thus ensuring 100% programming yield.

The erasable nature of these devices allows test programs to

be used and erased during early stages of the production flow.

The devices also contain on-board logic test circuitry to allow

verification of function and AC specification once encapsu-

lated in non-windowed packages.

or GND). Each set of V

192-Macrocell MAX

pin should be separately decoupled to GND, directly

•

and GND. For the most effective decoupling,

San Jose

CA 95134

and GND pins must be

or V

Revised April 9, 2004

•

OUT

) < V

408-943-2600

CY7C341

EPLD

. Unused

Related parts for CY7C341-25RC

CY7C341-25RC Summary of contents

Page 1

... LAB. Each LAB is interconnected with a programmable inter- connect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341 allows them to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips ...

Page 2

... LAB E MACROCELL 65 MACROCELL 66 MACROCELL 67 MACROCELL 68 MACROCELL 69–80 LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELL 89–96 3, 24, 45, 66 (B5, G2, K7, E10 GND CY7C341 7C341-30 7C341- 380 380 480 480 480 480 360 360 435 435 435 435 INPUT (C6) 84 INPUT ...

Page 3

... RSU DELAY LAD SYSTEM CLOCK DELAY t ICS CLOCK DELAY t IC LOGIC ARRAY DELAY t FD I/O DELAY t IO Figure 1. CY7C341 Internal Timing Model CY7C341 PGA Bottom View I/O I/O GND I/O INPUT I/O I/O I/O GND INPUT V I/O CC I/O INPUT INPUT I/O ...

Page 4

... C to +125 C (Case) Min. Max. 2.4 0.45 2 −0.3 0.8 −10 +10 −40 +40 −30 −90 Commercial 360 Military/Industrial 435 Commercial 380 Military/Industrial 480 100 100 Max 0.5V has been chosen to avoid test OUT CY7C341 ± ± 10% 5V ± 10% Unit 0 µA µ Unit pF pF Page ...

Page 5

... Com’l Mil Com’l Mil Com’l 15 Mil 15 Com’l 30 [8] Mil 30 should be added to the comparable delay for a dedicated input. If expanders are used, add the PIA CY7C341 ALL INPUT PULSES 3.0V 90% 10% GND < [6] 7C341-30 7C341-35 Max Min. Max Min. ...

Page 6

... Com’l 62 Mil 62.5 Com’l 62.5 Mil 62.5 Com’l 3 [3, 18] Mil the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within S1 CY7C341 [6] (continued) 7C341-30 7C341-35 Max Min. Max Min. Max 12.5 10 12 ...

Page 7

... If register output states must also control external points, this frequency can still be observed ACF AS1 AWH AWL . It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. ACO1 CY7C341 [6] (continued) 7C341-30 7C341-35 Max Min. Max Min ...

Page 8

... Mil 6 Com’l 6 Mil 6 Com’l 3 Mil 3 Com’l 1 Mil 1 [28] Com’l 3 Mil 3 Com’l 8 Mil 8 Com’l 8 Mil 8 14 Mil 14 Com’l 2 Mil 2 Com’l 1 Mil 1 Com’l 5 Mil 5 Com’l 5 Mil 5 CY7C341 7C341-30 7C341-35 Min. Max Min. Max ...

Page 9

... USE ULTRA37000™ FOR ALL NEW DESIGNS [2] Over the Operating Range (continued) 7C341-25 Min. Max Com’l 5 Mil 5 Com’l 5 Mil 5 Com’l 14 Mil t /t PD1 PD2 CO1 CO2 CY7C341 7C341-30 7C341-35 Min. Max Min. Max HIGH-IMPEDANCE 3-ST ATE VALID OUTPUT Page Unit ...

Page 10

... FROM ASYNCH. REGISTERED FEEDBACK Internal Combinatorial INPUT PIN I/O PIN EXPANDER ARRAY DELAY LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT Document #: 38-03034 Rev. *B USE ULTRA37000™ FOR ALL NEW DESIGNS AS1 ACO1 AOH ACO2 PIA EXP CY7C341 t t AWH AWL LAC LAD Page ...

Page 11

... RSU DATA FROM LOGIC ARRAY Internal Synchronous CLOCK FROM LOGIC ARRAY t RD DATA FROM LOGIC ARRAY OUTPUT PIN Document #: 38-03034 Rev. *B USE ULTRA37000™ FOR ALL NEW DESIGNS t AWL RSU LATCH FD t PIA ICS CY7C341 CLR PRE HIGH IMPEDANCE STATE Page ...

Page 12

... Ordering Information Speed (ns) Ordering Code 25 CY7C341-25HC/HI CY7C341-25JC/JI CY7C341-25RC/RI 30 CY7C341-30HC/HI CY7C341-30JC/JI CY7C341-30RC/RI CY7C341-30HMB CY7C341-30RMB 35 CY7C341-35HC/HI CY7C341-35JC/JI CY7C341-35RC/RI CY7C341-35HMB CY7C341-35RMB MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter CC1 Document #: 38-03034 Rev. *B USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type H84 ...

Page 13

... Package Diagrams Document #: 38-03034 Rev. *B USE ULTRA37000™ FOR ALL NEW DESIGNS 84-Leaded Windowed Leaded Chip Carrier H84 CY7C341 51-80081-** Page ...

Page 14

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 84-Lead Plastic Leaded Chip Carrier J83 84-Lead Windowed Pin Grid Array R84 CY7C341 51-85006-*A 51-80026-*B Page ...

Page 15

... Document History Page Document Title: CY7C341 192-Macrocell MAX® EPLD Document Number: 38-03034 REV. ECN NO. Issue Date ** 106379 06/18/01 *A 111355 12/17/01 *B 213375 See ECN Document #: 38-03034 Rev. *B USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV Change from Spec#: 38-00499 to 38-03034 ...

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