5962-9061102YA QP SEMICONDUCTOR, 5962-9061102YA Datasheet - Page 11

• Manufacturer Part Number: 5962-9061102YA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-9061102YA

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DSCC FORM 2234
APR 97
9/
10/ Transition is measured + 0.5 V from steady state voltage on the output from the 1.5 V level on the input with the load on
11/ This specification is a measure of the delay from synchronous register clock input to internal feedback of the register
12/ Values guaranteed by design and are not tested.
13/ This specification is a measure of the delay associated with the internal register feedback path. This delay plus the
14/ This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only
15/ This specification indicates the guaranteed maximum frequency at which a state machine with internal only feedback can
16/ This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin
17/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or
18/ This parameter indicates the minimum time after a synchronous register clock input that the previous register output data
19/ This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register
20/ This specification is a measure of the delay associated with the internal register feedback path for an asynchronous
21/ This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine
22/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with
23/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be
24/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be
25/ This parameter indicates the minimum time that the previous register output data is maintained on the output pin, after an
This parameter is the delay from an input signal applied to an I/O macrocell pin to any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through
the expander logic.
figure 3, circuit B.
output signal to a combinatorial output for which the registered output signal is used as an input. This parameter assumes
that no expanders are used in the logic of the combinatorial output and the register is synchronously clocked. (see figure 4)
register set-up time, t
feedback can operate.
operate. If register output states must also control external points, this frequency can still be observed as long as this
frequency is less than 1/t
to output pin). This assumes that no expander logic is used.
buried register can be cycled by a clock signal applied to either a dedicated input pin or an I/O pin.
is maintained on the output pin.
output signal to a combinatorial output for which the registered output signal is used as an input. Assumes no expanders
are used in logic of combinatorial output or the asynchronous clock input.
clocked register. This delay plus the asynchronous register setup time, t
asynchronously clocked state machine configuration. This delay assumes no expander logic in the asynchronous clock
path. (see figure 4)
configuration with external feedback can operate. It is assumed no expander logic is employed in the clock signal path or
data input path.
internal only feedback can operate. If register output states must also control external points, this frequency can still be
observed as long as this frequency is less than 1/t
cycled in asynchronously clocked mode. If this frequency is less than 1/(t
maximum frequency at which the device may operate in the asynchronously clocked data path mode. Assumes no
expander logic used.
cycled in asynchronously clocked mode by a clock signal applied to either a dedicated input or an I/O pin.
asynchronous register clock is input to an external dedicated input or I/O pin.
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
STANDARD
S
, is the minimum internal period for an internal state machine configuration.
CO1
TABLE I. Electrical performance characteristics - Continued.
. This specification assumes no expander logic is used.
ACO1
. This specification assumes no expander logic is utilized.
SIZE
A
AS
ACO1
, is the minimum internal period for an
) or 1/(t
REVISION LEVEL
AS
+ t
B
AH
). It also indicates the
SHEET
5962-90611
11