AT94S40AL-25BQX Atmel, AT94S40AL-25BQX Datasheet - Page 3
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AT94S40AL-25BQX
Manufacturer Part Number
AT94S40AL-25BQX
Description
Manufacturer
Atmel
Datasheet
1.AT94S40AL-25BQX.pdf
(32 pages)
Specifications of AT94S40AL-25BQX
Device System Gates
40000
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
Figure 1-1.
2314E–FPSLI–6/05
Configuration Logic
Configuration
EEPROM
and Chip
For ISP
Erase
I/O
AT94S Architecture
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing
powerful instructions in a single-clock-cycle, and allows system designers to optimize power
consumption versus processing speed. The AVR core is based on an enhanced RISC architec-
ture that combines a rich instruction set with 32 general-purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code-efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip
SRAM. Both the FPGA configuration SRAM and AVR instruction code SRAM are automatically
loaded at system power-up using Atmel’s in-system programmable AT17 Series EEPROM con-
figuration memories, which are part of the AT94S Multi-chip Module (MCM).
State-of-the-art FPSLIC design tools, System Designer, were developed in conjunction with the
FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller devel-
opment and debugging, FPGA development, place and route, and complete system
co-verification in one easy-to-use software tool.
SRAM Memory
Up to 16K x 16
Program
Address Lines
Decoded
Up to 16
5 - 40K Gates FPGA
PROGRAMMABLE I/O
Multiply
16K x 8
SRAM
Up to
with
Data
AT94S Secure Family
Timer/Counters
16 Prog. I/O
2-wire Serial
Two Serial
Two 8-bit
UARTs
Lines
Unit
4 Interrupt Lines
I/O
I/O
I/O
3