AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet
AT94K10AL-25DQC
Specifications of AT94K10AL-25DQC
Available stocks
Related parts for AT94K10AL-25DQC
AT94K10AL-25DQC Summary of contents
Page 1
Features • Monolithic Field Programmable System Level Integrated Circuit (FPSLIC – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Extensive Data and Instruction SRAM and JTAG ICE • 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM – ...
Page 2
... MHz 3.0 - 3.6V 1. FPSLIC parts with JTAG ICE support can be identified by the letter “J” after the device date code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Table 1 combination of the popular Atmel AT94K10AL AT94K40AL 10K 40K 576 2304 ...
Page 3
Figure 1-1. The AT94K series architecture is shown in Figure 1-2. 1138I–FPSLI–1/08 FPSLIC Device Date Code with JTAG ICE Support ® AT94K40AL-25DQC 0H1230 4201J Figure AT94K Series Architecture 5 - 40K Gates FPGA Addr Decoder Up to ...
Page 4
... Fast, Flexible and Efficient SRAM The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual- port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s macro generator tool. 2.2 ...
Page 5
... The Symmetrical Array At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells, see Figure ble by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM, with either synchronous or asynchronous operation. 1138I– ...
Page 6
The Busing Network Figure 2-1. Figure 2-2 resources: a local-bus resource (the middle bus) and two express-bus resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. Each local-bus ...
Page 7
Figure 2-2. 1138I–FPSLI–1/08 Busing Plane (One of Five) = AT40K Core Cell = Local/local or Express/express Turn Point = Row Repeater = Column AT94KAL Series FPSLIC 7 ...
Page 8
Cell Connections In Figure 2-3 neighbors. Section (b) of buses (one per busing plane) and five vertical local buses (one per busing plane). Figure 2-3. 2.8 The Cell Figure 2-4 muxes and pass gates are independent. All permutations of ...
Page 9
Figure 2-4. The Cell "1" "1" "1" LUT LUT OUT "0" "1" CLOCK RESET/SET ...
Page 10
Figure 2-5. Synthesis Mode Arithmetic Mode DSP/Multiplier Mode Counter Mode Tri-State/Mux Mode 2.9 RAM There are two types of RAM in the FPSLIC device: the FreeRAM distributed through the FPGA Core and the SRAM shared by the AVR and FPGA. ...
Page 11
RAM blocks. For the left-most RAM blocks, RAddr is on the left and WAddr is on the right. For the right-most RAM blocks, WAddr is on the left and RAddr is tied off. For single-ported RAM, ...
Page 12
Figure 2-7. FreeRAM Logic "1" 5 READ ADDR 5 WRITE ADDR WE 4 DATA IN Note: 1. For dual port, the switches on READ ADDR and DATA OUT would be on. The other two would be off. The reverse ...
Page 13
Figure 2-8. Note: 1138I–FPSLI–1/08 FreeRAM Example: 128 x 8 Dual-ported RAM (Asynchronous) 1. These layouts can be generated automatically using the Macro Generators. AT94KAL Series FPSLIC (1) 13 ...
Page 14
Clocking and Set/Reset Six of the eight dedicated Global Clock buses ( and 8) are connected to a dual-use Global Clock pin. In addition, two Global Clock buses (5 and 6) are driven from clock ...
Page 15
The FPGA clocks from the AVR are effected differently in the various sleep modes of the AVR, see Table The source clock into the FPGA GCK5 and GCK6 will determine what happens during the vari- ous power-down modes of the ...
Page 16
Figure 2-10. Clocking (for One Column of Cells) Note: AT94KAL Series FPSLIC 16 Express Bus (Plane 4; Half Length at Edge) Repeater 1. Two on left edge column of the embedded FPGA array only. (1) FCK } } GCK1 − ...
Page 17
Figure 2-11. Set/Reset (for One Column of Cells) (Plane 5; Half Length at Edge) Some of the bus resources on the embedded FPGA core are used as dual-function resources. Table 2-2 The FPGA software tools are designed to automatically accommodate ...
Page 18
Table 2-2. Function Cell Output Enable FreeRAM Output Enable FreeRAM Write Enable FreeRAM Address FreeRAM Data In FreeRAM Data Out Clocking Set/Reset Figure 2-12. Primary I/O PULL-DOWN AT94KAL Series FPSLIC 18 Dual-function Buses Type Plane(s) Local 5 Express 2 Express ...
Page 19
Figure 2-13. Secondary I/O PULL-UP PAD PULL-DOWN Figure 2-14. Primary and Secondary I/ secondary I primary I/O 1138I–FPSLI–1/08 AT94KAL Series FPSLIC "0" "1" "0" "1" cell cell ...
Page 20
Figure 2-15. Corner I/Os VCC DRIVE TRI-ST ATE PULL-UP PAD PULL-DOWN AT94KAL Series FPSLIC 20 PAD GND VCC TTL/CMOS DRIVE SCHMITT TRI-ST ATE DELAY CLK RST RST CLK "0" "1" "0" "1" PAD GND TTL/CMOS SCHMITT DELAY CLK RST RST ...
Page 21
FPGA/AVR Interface and System Control The FPGA and AVR share a flexible interface which allows for many methods of system integration. • Both FPGA and AVR share access to the 15 ns dual-port SRAM. • The AVR data bus ...
Page 22
Program and Data SRAM Kbytes dual-port SRAM reside between the FPGA and the AVR. This SRAM is used by the AVR for program instruction and general-purpose data storage. The AVR is con- nected ...
Page 23
Figure 3-2. $3FFF $3000 $2FFF $2000 $1FFF $1000 $0FFF $005F $001F $0000 Notes: 1138I–FPSLI–1/08 FPSLIC Configurable Allocation SRAM Memory Memory Partition is User Defined during Development Data SRAM Memory OPTIONAL 4 Kbytes x 8 OPTIONAL 4 Kbytes x 8 OPTIONAL ...
Page 24
Data SRAM Access by FPGA – FPGAFrame Mode The FPGA user logic has access to the data SRAM directly through the FPGA side of the dual- port memory, see “System Control Register – FPGA/AVR” on page abled during configuration ...
Page 25
A Side The A side is partitioned into Program memory and Data memory: • Program memory is 16-bit words. • Program memory address $0000 always starts in the highest two SRAMs ( [SRAMn - 1 (low ...
Page 26
Table 3-2. 3.4.3 B Side The B side is not partitioned; the FPGA (and AVR debug mode) views the memory space Kbytes. • The B side is accessed by the FPGA/Configuration Logic. • The B side ...
Page 27
Table 3-3. SRAM 00 01 (1) 02 (1) 03 (1) 04 (1) 05 ( Note: Example: Frame (and AVR debug mode) write of instructions to ...
Page 28
Figure 3-4. (REGISTERED) Figure 3-5. CLOCK RAMRE RAMADR AT94KAL Series FPSLIC 28 AVR SRAM Data Memory Write Using “ST” Instruction CLOCK RAMWE RAMADR DBUS VALID DBUSOUT ST cycle 1 AVR SRAM Data Memory Read Using “LD” Instruction DBUS LD cycle ...
Page 29
... FPGA, thereby affecting a download, or allowing reconfigurable systems where the FPGA is updated algorithmically by the AVR. For more infor- mation, refer to the “AT94K Series Configuration” application note available on the Atmel web site, at: http://www.atmel.com/atmel/acrobat/doc2313.pdf. 3.6 ...
Page 30
System Control 3.7.1 Configuration Modes The AT94K family has four configuration modes controlled by mode pins M0 and M2, see 3-6. Table 3- Modes 2 and 3 are reserved and are used for factory ...
Page 31
Table 3-7. Bit SCR5 SCR6 SCR7 - SCR12 SCR13 SCR14 - SCR15 SCR16 - SCR23 SCR24 - SCR25 SCR26 SCR27 SCR28 - SCR29 SCR30 1138I–FPSLI–1/08 FPSLIC System Control Register (Continued) Description Reserved 0 = OTS Disabled 1 = OTS Enabled ...
Page 32
Table 3-7. Bit SCR31 SCR32 - SCR34 SCR35 SCR36 SCR37 SCR38 SCR39 SCR40 - SCR41 SCR 42 - SCR47 SCR48 SCR49 SCR50 SCR51 SCR52 SCR53 AT94KAL Series FPSLIC 32 FPSLIC System Control Register (Continued) Description 0 = Disable I/O Tri-state ...
Page 33
Table 3-7. Bit SCR54 SCR55 SCR56 SCR57 SCR58 - SCR59 SCR60 - SCR61 SCR62 SCR63 1138I–FPSLI–1/08 FPSLIC System Control Register (Continued) Description 0 = AVR Port D I/O With 6 mA Drive 1 = AVR Port D I/O With 20 ...
Page 34
AVR Core and Peripherals • AVR Core • Watchdog Timer/On-chip Oscillator • Oscillator-to-Internal Clock Circuit • Oscillator-to-Timer/Counter for Real-time Clock • 16-bit Timer/Counter and Two 8-bit Timer/Counters • Interrupt Unit • Multiplier • UART (0) • UART (1) • ...
Page 35
... Instruction Set Nomenclature (Summary) The complete “AVR Instruction Set” document is available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0856.pdf. 4.1.1 Status Register (SREG) SREG 4.1.2 Registers and Operands Rd: Rr X,Y, 4.1.3 I/O Registers 4.1.3.1 Stack STACK: SP: 4.1.3.2 Flags ⇔ The instructions EIJMP, EICALL, ELPM, GPM, ESPM (from the megaAVR Instruction Set) are not supported in the FPSLIC device. 1138I– ...
Page 36
Table 4-1. Conditional Branch Summary Test Boolean Mnemonic Z•(N ⊕ > Rr BRLT Rd ≥ ⊕ BRGE BREQ Rd ≤ Rr Z+(N ⊕ ...
Page 37
Table 4-2. Instruction Set Summary (Continued) Mnemonics Operands Description INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed ...
Page 38
Table 4-2. Instruction Set Summary (Continued) Mnemonics Operands Description BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than, Signed BRHS ...
Page 39
Table 4-2. Instruction Set Summary (Continued) Mnemonics Operands Description STD Y+q, Rr Store Indirect with Displacement Store Indirect ST Z+, Rr Store Indirect and Post-Increment ST -Z, Rr Store Indirect and Pre-Decrement STD Z+q, Rr Store Indirect ...
Page 40
Table 4-2. Instruction Set Summary (Continued) Mnemonics Operands Description SEV Set Two’s Complement Overflow CLV Clear Two’s Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in ...
Page 41
RX1 Input (receive) to UART(1) – See SCR53 4.3.8 TX1 Output (transmit) from UART(1) – See SCR53 4.3.9 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 4.3.10 XTAL2 Output from the inverting ...
Page 42
External Clock To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 4-2. 4.4.3 No Clock/Oscillator Source When not in use, for low static IDD, add a ...
Page 43
Architectural Overview The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program memory is accessed with a single level pipeline. While one instruction is being executed, the next instruction is ...
Page 44
General-purpose Register File Figure 4-5 Figure 4-5. General-purpose Working Registers All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, ...
Page 45
X-register, Y-register and Z-register Registers R26..R31 have some added functions to their general-purpose usage. These registers are address pointers for indirect addressing of the SRAM. The three indirect address registers X, Y and Z have functions as fixed displacement, ...
Page 46
Data Direct A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to ...
Page 47
Figure 4-6. 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-7 operation using two register operands is executed, and the result is stored back to the ...
Page 48
Memory-mapped I/O The I/O space definition of the embedded AVR core is shown in the following table: 4.11.1 AT94K Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 $3C ($5C) ...
Page 49
... UART1 Baud-rate Register Note: 1. The On-chip Debug Register (OCDR) is detailed on the “FPSLIC On-chip Debug System” distributed within Atmel and select third-party vendors only under Non-Disclosure Agreement (NDA). Contact fpslic@atmel.com for a copy of this document. The embedded AVR core I/Os and peripherals, and all the virtual FPGA peripherals are placed in the I/O space ...
Page 50
Figure 4-9. For single-cycle access (In/Out Commands) to I/O, the instruction has to be less than 16 bits: In the data SRAM, the registers are located at memory addresses $00 - $1F and the I/O space is located at memory ...
Page 51
Status Register – SREG The AVR status register BitM $3F ($5F) Read/Write Initial Value Note: • Bit Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual ...
Page 52
Stack Pointer – SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). Future versions of FPSLIC may support up to 64K Bytes of memory; ...
Page 53
When this bit is set to 1, the AVR can write its own program SRAM. During AVR reset, the DBG bit is cleared by the hardware. • Bit 0 - SRST: Software Reset When this bit is set (one), a ...
Page 54
Bit 0 - EXTRF: External (Software) Reset Flag This flag is set (one) in three separate circumstances: power-on reset, use of Resetn/AVRRe- setn and writing a one to the SRST bit in the Software Control Register – SFTCR. The ...
Page 55
FPGA I/O Selection by AVR Sixteen select signals are sent to the FPGA for I/O addressing. These signals are decoded from four I/O registry addresses (FISUA...D) and extended to sixteen with two bits from the FPGA I/O Select Control ...
Page 56
Table 4-4. Read or Write I/O Address FISUA $14 ($34) FISUB $15 ($35) FISUC $16 ($36) FISUD $17 ($37) Note: In summary, 16 select signals are sent to the FPGA for I/O addressing. These signals are decoded from four base ...
Page 57
General AVR/FPGA I/O Select Procedure I/O select depends on the FISCR register setup and the FISUA..D register written to or read from. The following FISCR setups and writing data to the FISUA..D registers will result in the shown I/O ...
Page 58
Figure 4-10. Out Instruction – AVR Writing to the FPGA Note: Figure 4-11. In Instruction – AVR Reading FPGA AVR CLOCK (FISUA (FPGA DATA OUT) Notes: AT94KAL Series FPSLIC 58 AVR INST OUT INSTRUCTION AVR CLOCK ...
Page 59
FPGA I/O Interrupt Control by AVR This is an alternate memory space for the FPGA I/O Select addresses. If the FIADR bit in the FISCR register is set to logic 1, the four I/O addresses, FISUA - FISUD, are ...
Page 60
Bits 3..0 - FINT11 - 8: FPGA Interrupt Masks See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks Not available on the AT94K05. • Bits 3..0 - FINT15 - 12: FPGA Interrupt ...
Page 61
Table 4-6. Vector No. (hex) 1138I–FPSLI–1/08 Reset and Interrupt Vectors (Continued) Program Address Source 11 $0020 TIM0_OVF 12 $0022 FPGA_INT4 13 $0024 FPGA_INT5 14 $0026 FPGA_INT6 15 $0028 FPGA_INT7 16 $002A UART0_RXC 17 $002C UART0_DRE 18 $002E UART0_TXC 19 $0030 ...
Page 62
The most typical program setup for the Reset and Interrupt Vector Addresses are: Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E $0030 $0032 ...
Page 63
Reset Sources The embedded AVR core has five sources of reset: • External Reset. The MCU is reset immediately when a low-level is present on the RESET or AVR RESET pin. • Power-on Reset. The MCU is reset upon ...
Page 64
Table 4-7. Symbol V POT(1) V RST T TOUT Note: 4.16.2 Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 4-12, an internal timer clocked from the Watchdog Timer oscillator ...
Page 65
The MCU after five CPU clock-cycles, and can be used when an external clock signal is applied to the XTAL1 pin. This setting does not use the WDT oscillator, and enables very fast start-up from the Sleep, Power-down or Power-save ...
Page 66
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions ...
Page 67
Bit 5 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed ...
Page 68
Bit 6 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by the hardware when exe- ...
Page 69
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine ...
Page 70
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the ...
Page 71
... The AVR IEEE std. 1149.1 compliant JTAG interface is used for on-chip debugging. The On-Chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Figure 4-16 TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift register) between the TDI - input and TDO - output ...
Page 72
When the JTAGEN bit is unprogrammed, these four TAP pins revert to normal operation. When programmed, the input TAP signals are internally pulled High and the JTAG is enabled for Boundary-Scan. System Designer sets this bit by default. For the ...
Page 73
Figure 4-17. TAP Controller State Diagram 1 0 1138I–FPSLI–1/08 Test-Logic-Reset 0 1 Run-Test/Idle Select-DR Scan 1 Capture-DR Shift-DR Exit1-DR Pause-DR 0 Exit2-DR Update-DR 1 AT94KAL Series FPSLIC 1 Select-IR Scan Capture- Shift- ...
Page 74
TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary- Scan circuitry and On-Chip Debug system. The state transitions depicted in on the signal present on TMS (shown adjacent to each ...
Page 75
... The AVR Studio enables the user to fully control execution of programs on an AVR device with On-Chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simula- tor. AVR Studio supports source level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third-party vendors’ compilers. ...
Page 76
... On-chip Debug Specific JTAG Instructions The On-Chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Table 4-8. JTAG Instruction EXTEST IDCODE SAMPLE_PRELOAD RESERVED PRIVATE PRIVATE PRIVATE RESERVED PRIVATE PRIVATE PRIVATE PRIVATE AVR_RESET ...
Page 77
ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and ...
Page 78
... Part Number The part number bit code identifying the component. The JTAG Part Number for AVR devices is listed in Table 4-10. Device AT94K05 AT94K10 AT94K40 Manufacturer ID The manufacturer ID for ATMEL is 0x01F (11 bits). AT94KAL Series FPSLIC 78 shows the structure of the Device Identification register. MSB ...
Page 79
AVR Reset Register The AVR Reset Register is a Test Data Register used to reset the AVR. A high value in the Reset Register corresponds to pulling the external AVRResetn Low. The AVR is reset as long as there ...
Page 80
Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain. • Shift-DR: The Internal Scan Chain is shifted by the TCK input. • Update-DR: Data from the scan chain is applied to output pins. 4.22.2.2 IDCODE; $1 ...
Page 81
Figure 4-20. Boundary-scan Cell For Bi-directional Port Pin with Pull-up Function Pullup Disable (PLD) Output Control (OC) Output Data (OD Input Data (ID) From Last Cell 1138I–FPSLI–1/08 ShiftDR To Next Cell FF2 FF1 0 ...
Page 82
Figure 4-21 The Boundary-Scan details from Figure 4-21. General Port Pin Schematic Diagram AT94KAL Series FPSLIC 82 shows a simple digital Port Pin as described in the section Figure 4-20 PLD PULL- PXn ID WP: WRITE PORTX WD: ...
Page 83
When no alternate port function is present, the Input Data - ID corresponds to the PINn register value, Output Data corresponds to the PORTn register, Output Control corresponds to the Data Direction (DDn) register, and the PuLL-up Disable (PLD) corresponds ...
Page 84
Scanning 2-wire Serial The SCL and SDA pins are open drain, bi-directional and enabled separately. The “Enable Out- put” bits (active High) in the scan chain are supported by general boundary-scan cells. Enabling the output will drive the pin ...
Page 85
Scanning an oscillator output gives unpredictable results as there is a frequency drift between the internal oscillator and the JTAG TCK clock. The clock configuration is programmed in the SCR SCR bit is not changed run-time, the clock ...
Page 86
Table 4-11. I/O Ports EXT. INTERRUPTS AT94KAL Series FPSLIC 86 AVR I/O Boundary Scan – JTAG Instructions $0/$2 (Continued) PORTD UART1 UART0 XTAL Description Bit Data Out/In - PD7 44 Enable Output - PD7 43 Pull-up - PD7 42 Data ...
Page 87
Table 4-11. 2-wire Serial Notes: Table 4-12. Input with Pull-up - INTPn Input with Pull-up - RXn Enable Clock - XTAL 1 1138I–FPSLI–1/08 AVR I/O Boundary Scan – JTAG Instructions $0/$2 (Continued) I/O Ports TOSC (2) 1. Observe-only scan cell. ...
Page 88
Table 4-12. Enable Clock - TOSC 1 Enable Output - SDA 4.22.5 Boundary-scan Description Language Files Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices in a standard format used by automated test-generation software. The order and function of bits ...
Page 89
Timer/Counters The FPSLIC provides three general-purpose Timer/Counters: two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external oscillator. This oscil- lator is optimized for use with a 32.768 kHz watch crystal, enabling use ...
Page 90
Figure 4-26. Timer/Counter2 Prescaler TOSC1 Special Function I/O Register – SFIOR Bit $30 ($50) Read/Write Initial Value • Bits 7..2 - Res: Reserved Bits These bits are reserved bits in the FPSLIC and are always read as zero. • Bit ...
Page 91
Figure 4-27. Timer/Counter0 Block Diagram Figure 4-28. Timer/Counter2 Block Diagram 1138I–FPSLI–1/08 T/C0 OVER- T/C0 COMPARE FLOW IRQ MATCH IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C CLEAR TIMER/COUNTER0 T/C CLK SOURCE (TCNT0) UP/DOWN 7 ...
Page 92
The 8-bit Timer/Counter0 can select the clock source from CK, prescaled CK external pin. The 8-bit Timer/Counter2 can select the clock source from CK, prescaled CK or external TOSC1. Both Timers/Counters can be stopped as described in section ...
Page 93
Bit 6 - PWM0/PWM2: Pulse Width Modulator Enable When set (one) this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on • Bits 5,4 - COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0 ...
Page 94
Table 4-13. CS02 Table 4-14. CS22 The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the CK oscillator ...
Page 95
Both Timer/Counters are realized up/down (in PWM mode) counters with read and write access. If the Timer/Counter is written to and a clock source is selected, it continues counting in the timer clock cycle following the write ...
Page 96
Table 4-15. (1) CTCn ( Notes: In PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into the OCR when the Timer/Counter ...
Page 97
Figure 4-29. Effects of Unsynchronized OCR Latching in Up/Down Mode Compare Value Changes Note: Figure 4-30. Effects of Unsynchronized OCR Latching in Overflow Mode. Note: During the time between the write and the latch operation, a read from the Output ...
Page 98
Table 4-16. COMn1 Notes: In up/down PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal Timer/Counter mode. Timer Overflow ...
Page 99
If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2 and ...
Page 100
Therefore, the contents of all Timer2 registers must be considered lost after a wake-up from power-down, due to the ...
Page 101
Timer/Counter1 Figure 4-31 Figure 4-31. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE FLOW IRQ MATCHA IRQ TIMER INT. MASK REGISTER (TIMSK T/C1 INPUT CAPTURE REGISTER (ICR1 TIMER/COUNTER1 (TCNT1 BIT COMPARATOR 15 8 ...
Page 102
Timer/Counter1 useful for lower speed functions or exact-timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare Regis- ter 1 A and B – OCR1A and OCR1B as the data sources to be compared ...
Page 103
Table 4-17. COM1X1 Notes: • Bit 3 - FOC1A: Force Output Compare1A Writing a logic 1 to this bit forces a change in the compare match output pin PE6 according to the values already set in ...
Page 104
Timer/Counter1 Control Register B – TCCR1B Bit $2E ($4E) Read/Write Initial Value • Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis- abled. ...
Page 105
Table 4-19. CS12 The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter1, ...
Page 106
The Timer/Counter1 is realized up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 con- tinues counting in the timer clock-cycle after it ...
Page 107
Timer/Counter1 Input Capture Register – ICR1H AND ICR1L Bit $25 ($45) $24 ($44) Read/Write Initial Value The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting – ICES1) ...
Page 108
Table 4-20. CTC1 Table 4-21. (1) OTC1 ( Notes: In the PWM mode, the least significant OCR1A/OCR1B bits (depends of resolution), when written, are transferred ...
Page 109
Figure 4-33. Effects on Unsynchronized OCR1 Latching Compare Value Changes Note: Figure 4-34. Effects of Unsynchronized OCR1 Latching in Overflow Mode Note: During the time between the write and the latch operation, a read from OCR1A or OCR1B will read ...
Page 110
Table 4-22. COM1X1 Notes: In up/down PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. In overflow PWM mode, the Timer Overflow flag is set as in normal Timer/Counter mode. Timer Overflow Interrupt1 operates ...
Page 111
Watchdog Timer Control Register – WDTCR Bit $21 ($41) Read/Write Initial Value • Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the FPSLIC and will always read as zero. • Bit 4 - WDTOE: Watchdog Turn-off ...
Page 112
Multiplier The multiplier is capable of multiplying two 8-bit numbers, giving a 16-bit result using only two clock cycles. The multiplier can handle both signed and unsigned integer and fractional numbers without speed or code size penalty. Below are ...
Page 113
Table 4-24. 8-bit x 8-bit Routines: Unsigned Multiply bits Signed Multiply bits Fractional Signed/Unsigned Multiply bits Fractional Signed Multiply-accumulate ...
Page 114
Example 1 – Basic Usage The first example shows an assembly code that reads the port B input value and multiplies this value with a constant (5) before storing the result in register pair R17:R16. in ldi mul movw ...
Page 115
Example 3 – Multiply-accumulate Operation The final example of 8-bit multiplication shows a multiply-accumulate operation. The general for- mula can be written as ldi muls r19,r18 ; r1:r0 = variable A * variable B ...
Page 116
Operation This operation is valid for both unsigned and signed numbers, even though only the unsigned multiply instruction (MUL) is needed, see When A and B are positive numbers least one of ...
Page 117
Operation 4.28.4.1 Example 4 – Basic Usage 16-bit x 16-bit = 32-bit Integer Multiply Below is an example of how to call the multiply subroutine. This is also illustrated ...
Page 118
Multiply-accumulate Operation Figure 4-40. 16-bit Multiplication, 32-bit Accumulated Result 4.28.6 Using Fractional Numbers Unsigned 8-bit fractional numbers use a format where numbers in the range [0, 2> are allowed. Bits represent the fraction and bit ...
Page 119
Table 4-25. Bit Number Using the FMUL, FMULS and FMULSU instructions should not be more complex than the MUL, MULS and MULSU instructions. However, one potential problem is to assign fractional variables right values in a simple way. The fraction ...
Page 120
Since we do not have a rest, the remaining three bits will be zero, and the final result is “1110 1000”, which 0.5 + 0.25 + 0.0625 = 1.8125. To convert a negative fractional number, first add ...
Page 121
The registers R19:R18:R17:R16 will be incremented with the result of the multiplication of 0.771484375 with the ADC conversion result. In this example, the ADC result is treated as a signed fraction number. We could also treat signed ...
Page 122
Description Unsigned multiply of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 = R23:R22 • R21:R20 Statistics Cycles ret Words ret Register usage and R16 to R23 (11 registers) Note: ...
Page 123
Description Signed multiply of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 = R23:R22 • R21:R20 Statistics Cycles ret Words ret Register usage and R16 to R23 (11 registers) Note: ...
Page 124
Description Signed multiply-accumulate of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 += R23:R22 • R21:R20 Statistics Cycles ret Words ret Register usage and R16 to R23 (11 registers) mac16x16_32: ...
Page 125
Sign extend add r17, r0 adc r18, r1 adc ...
Page 126
Description Signed fractional multiply of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 = (R23:R22 • R21:R20) << 1 Statistics Cycles ret Words ret Register usage and R16 to R23 ...
Page 127
Description Signed fractional multiply-accumulate of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 += (R23:R22 • R21:R20) << 1 Statistics Cycles ret Words ret Register usage and R16 to R23 ...
Page 128
Comment on Implementations All 16-bit x 16-bit = 32-bit functions implemented here start by clearing the R2 register, ...
Page 129
UARTs The FPSLIC features two full duplex (separate receive and transmit registers) Universal Asyn- chronous Receiver and Transmitter (UART). The main features are: • Baud-rate Generator Generates any Baud-rate • High Baud-rates at Low XTAL Frequencies • ...
Page 130
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Regis- ter, UDRn. Data is transferred from UDRn to the Transmit shift register when: • A new character has been written to UDRn after ...
Page 131
Data Reception Figure 4-42 Figure 4-42. UART Receiver XTAL Note: The receiver front-end logic samples the signal on the RXDn pin at a frequency 16 times the baud-rate. While the line is idle, one single sample of logic 0 ...
Page 132
If however, a valid start bit is detected, sampling of the data bits following the start bit is per- formed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of ...
Page 133
Multi-processor Communication Mode The Multi-processor Communication Mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address byte to find out which MCU has been addressed particular Slave ...
Page 134
UART0 Control and Status Registers – UCSR0A Bit $0B ($2B) Read/Write Initial Value UART1 Control and Status Registers – UCSR1A Bit $02 ($22) Read/Write Initial Value • Bit 7 - RXC0/RXC1: UART Receive Complete This bit is set (one) when ...
Page 135
This bit is set if an Overrun condition is detected, i.e., when a character already present in the UDRn register is not read before the next character has been shifted into the Receiver Shift reg- ister. The ORn bit is ...
Page 136
Bit 3 - TXEN0/TXEN1: Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character ...
Page 137
Table 2. UBR Settings at Various Crystal Frequencies Clock UBRRHI UBR MHz 7:4 or 3:0 UBRRn HEX UBR 1 0000 00011001 019 0000 00001100 00C 0000 00000110 006 0000 00000011 003 0000 00000010 002 0000 00000001 001 0000 00000001 001 ...
Page 138
UART0 Baud-rate Register Low Byte – UBRR0 Bit $09 ($29) Read/Write Initial Value UART1 Baud-rate Register Low Byte – UBRR1 Bit $00 ($20) Read/Write Initial Value UBRRn stores the 8 least significant bits of the UART baud-rate register. 4.29.6 Double ...
Page 139
See UBR settings at various crystal frequencies in double UART speed mode. Table ...
Page 140
Serial Interface (Byte Oriented) The 2-wire Serial Bus is a bi-directional two-wire serial communication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and ...
Page 141
Figure 4-47. Block diagram of the 2-wire Serial Bus Interface The CPU interfaces with the 2-wire Serial Interface via the following five I/O registers: the 2-wire Serial Bit-rate Register (TWBR), the 2-wire Serial Control Register (TWCR), the 2-wire Serial Status ...
Page 142
Bits 7..0 - 2-wire Serial Bit-rate Register TWBR selects the division factor for the bit-rate generator. The bit-rate generator is a frequency divider which generates the SCL clock frequency in the Master modes according to the following equation: • ...
Page 143
Bit 4 - TWSTO: 2-wire Serial Bus STOP Condition Flag TWSTO is a stop condition flag. In Master mode, setting the TWSTO bit in the control register will generate a STOP condition on the 2-wire Serial Bus. When the ...
Page 144
The 2-wire Serial Data Register – TWDR Bit $1F ($3F) Read/Write Initial Value • Bits 7..0 - TWD: 2-wire Serial Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on ...
Page 145
Serial Modes The 2-wire Serial Interface can operate in four different modes: • Master Transmitter • Master Receiver • Slave Receiver • Slave Transmitter Data transfer in each mode of operation is shown in contain the following abbreviations: ...
Page 146
Serial Transfer can continue. The TWINT flag is cleared by writing a logic 1 to the flag. When the Slave address and the direction bit have been transmitted and an acknowledgment bit has been ...
Page 147
TWEN must be set to enable the 2-wire Serial Interface. The TWEA bit must be set to enable the acknowledgment of the device’s own Slave address or the general call address. TWSTA and TWSTO must be cleared. When TWAR and ...
Page 148
Miscellaneous States There are two status codes that do not correspond to a defined 2-wire Serial Interface state: Sta- tus $F8 and Status $00, see Status $F8 indicates that no relevant information is available because the 2-wire Serial Interrupt ...
Page 149
Table 4-29. Status Codes for Master Transmitter Mode Status Status of the 2-wire Code Serial Bus and 2-wire (TWSR) Serial Hardware A START condition $08 Load SLA+W has been transmitted Load SLA repeated START $10 condition has been ...
Page 150
Figure 4-48. Formats and States in the Master Transmitter Mode Successfull S SLA transmission to a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data ...
Page 151
Table 4-30. Status Codes for Master Receiver Mode Status Status of the 2-wire Code Serial Bus and 2-wire (TWSR) Serial Hardware A START condition has $08 been transmitted A repeated START $10 condition has been transmitted Arbitration lost in $38 ...
Page 152
Figure 4-49. Formats and States in the Master Receiver Mode Successfull S SLA reception from a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or ...
Page 153
Table 4-31. Status Codes for Slave Receiver Mode Status Status of the 2-wire Code Serial Bus and 2-wire (TWSR) Serial Hardware Own SLA+W has been $60 received; ACK has been returned Arbitration lost in SLA+R/W as Master; $68 own SLA+W ...
Page 154
Table 4-31. Status Codes for Slave Receiver Mode (Continued) Status Status of the 2-wire Code Serial Bus and 2-wire (TWSR) Serial Hardware Previously addressed Read data byte or with general call; data $90 has been received; Read data byte ACK ...
Page 155
Figure 4-50. Formats and States in the Slave Receiver Mode Reception of the own S slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as ...
Page 156
Table 4-32. Status Codes for Slave Transmitter Mode Status Status of the 2-wire Code Serial Bus and 2-wire (TWSR) Serial Hardware Load data byte or Own SLA+R has been $A8 received; ACK has been returned Load data byte Arbitration lost ...
Page 157
Figure 4-51. Formats and States in the Slave Transmitter Mode Reception of the own S slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. From master to slave From ...
Page 158
I/O Ports All AVR ports have true read-modify-write functionality when used as general I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI ...
Page 159
Table 4-34. DDDn Note: Figure 4-52. PortD Schematic Diagram 4.31.2 PortE PortE is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the PortE, one each for the ...
Page 160
Table 4-35. Port Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 When the pins are used for the alternate function the DDRE and PORTE register has to be set according to the alternate function description. PortE Data Register – ...
Page 161
LowPortE as General Digital I/O PEn, General I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero), ...
Page 162
This function happens only if the Check pin has been enabled in the sys- tem control register. The use of the Check pin will NOT disable the use of that pin as an input to PE7 nor as ...
Page 163
Figure 4-54. PortE Schematic Diagram (Pin PE1) 1138I–FPSLI–1/08 MOS PULL-UP DL RESET GTS PE1 MOS PULL- RX0 AT94KAL Series FPSLIC RESET Q DDE1 DL WD SCR(52) 0 RESET OC0/PMW0 1 Q PORTE1 COM00 COM01 WL RP GTS: Global ...
Page 164
Figure 4-55. PortE Schematic Diagram (Pin PE2) AT94KAL Series FPSLIC 164 MOS PULL-UP DL RESET GTS PE2 RP MOS PULL-UP DL RESET GTS TX1 TX1D RD RESET R Q DDE2 DL WD TX1ENABLE SCR(53 TX1D RESET R 1 ...
Page 165
Figure 4-56. PortE Schematic Diagram (Pin PE3) 1138I–FPSLI–1/08 MOS PULL-UP DL RESET GTS PE3 SCR(53) MOS PULL- RX1 AT94KAL Series FPSLIC RD RESET R Q DDE3 DL WD SCR(53 RESET R OC2/PMW2 1 Q PORTE3 COM20 ...
Page 166
Figure 4-57. PortE Schematic Diagram (Pin PE4) AT94KAL Series FPSLIC 166 MOS PULL-UP DL RESET GTS PE4 MOS PULL- INTP0 RD RESET R Q DDE4 DL WD SCR(48) RL RESET R Q PORTE4 SCR(48) GTS: ...
Page 167
Figure 4-58. PortE Schematic Diagram (Pin PE5) 1138I–FPSLI–1/08 MOS PULL-UP DL RESET GTS PE5 MOS PULL- INTP1 AT94KAL Series FPSLIC RD RESET R Q DDE5 DL WD SCR(49 RESET R OC1B 1 Q PORTE5 COM1B0 COM1B1 ...
Page 168
Figure 4-59. PortE Schematic Diagram (Pin PE6) AT94KAL Series FPSLIC 168 MOS PULL-UP DL RESET GTS PE6 MOS PULL- INTP2 RD RESET R Q DDE6 DL WD SCR(50 RESET R OC1A 1 Q PORTE6 COM1A0 COM1A1 ...
Page 169
Figure 4-60. PortE Schematic Diagram (Pin PE7) 1138I–FPSLI–1/08 MOS PULL-UP DL RESET GTS PE7 MOS PULL- INTP3 AT94KAL Series FPSLIC RD RESET Q DDE7 DL WD SCR(51) RL RESET Q PORTE7 WL RP ICP SCR(51) GTS: Global Tri-State ...
Page 170
AC & DC Timing Characteristics 5.1 Absolute Maximum Ratings* Operating Temperature................................. -55° +125° C Storage Temperature .................................... -65 ° +150° C (2) Voltage on Any Pin with Respect to Ground .....................................-0.5V to +5.0V Supply Voltage ...
Page 171
DC Characteristics – 3.3V Operation – Commercial/Industrial (Preliminary -40° 85° 2.7V to 3.6V (unless otherwise noted A CC Symbol Parameter V High-level Input Voltage IH V Input High-voltage IH1 V Input High-voltage ...
Page 172
... Atmel FPGAs require a minimum rated power supply current capacity to insure proper initializa- tion, and the power supply ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. Table 6-1. Device AT94K05AL AT94K10AL AT94K40AL Notes: AT94KAL Series FPSLIC 172 Power-On Power Supply Requirements ...
Page 173
FPSLIC Dual-port SRAM Characteristics The Dual-port SRAM operates in single-edge clock controlled mode during read operations, and a double-edge controlled mode during write operations. Addresses are clocked internally on the rising edge of the clock signal (ME). Any change ...
Page 174
Frame Interface The FPGA Frame Clock phase is selectable (see page 30). This document refers to the clock at the FPGA/Dual-port SRAM interface as ME (the relation data, address and write enable does not change). By ...
Page 175
Table 6-4. FPSLIC Interface Timing Information Symbol Parameter Clock Delay From XTAL2 Pad t IXG4 to GCK_5 Access to FPGA Core Clock Delay From XTAL2 Pad t IXG5 to GCK_6 Access to FPGA Core Clock Delay From XTAL2 Pad t ...
Page 176
... External Clock Drive 3.0V to 3.6V CC Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time 1. For AT94K05AL and AT94K10AL, the maximum oscillator frequency is 25 MHz. For AT94K40AL, the maximum oscillator frequency is 18 MHz. Minimum Maximum (1) 0 25/18 40 – 15 – ...
Page 177
AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
Page 178
AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
Page 179
AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
Page 180
... PXZ CMOS buffer delays are measured from a V stant. Buffer delay pad voltage of 1.5V with one output switching. Parameter based on characterization and simulation; not tested in production. An FPGA power calculation is available in Atmel’s System Designer software (see also page 171). AT94KAL Series FPSLIC 180 = 3.0V, temperature = 70° ...
Page 181
... Packaging and Pin List Information FPSLIC devices should be laid out to support a split power supply for both AL and AX families. Please refer to the “Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices” application note, available on the Atmel web site. Table 7-1. Part # ...
Page 182
Table 7-3. AT94K05 96 FPGA I/O I/O7 I/O8 GND I/O9, FCK1 I/O10 I/O11 (A20) I/O12 (A21) Notes: AT94KAL Series FPSLIC 182 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O I/O11 I/O12 (1) VCC GND I/O13 I/O14 ...
Page 183
Table 7-3. AT94K05 96 FPGA I/O I/O13 I/O14 I/O15 (A22) I/O16 (A23) GND VDD I/O17 (A24) I/O18 (A25) I/O19 I/O20 Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O I/O38 I/O39 I/O40 I/O19 I/O41 I/O20 ...
Page 184
Table 7-3. AT94K05 96 FPGA I/O I/O21 (A26) I/O22 (A27) I/O23 I/O24, FCK2 GND I/O25 I/O26 I/O27 (A28) I/O28 I/O29 I/O30 Notes: AT94KAL Series FPSLIC 184 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O GND I/O31 ...
Page 185
Table 7-3. AT94K05 96 FPGA I/O I/O31 (OTS) I/O32, GCK2 (A29) AVRRESET GND M0 VCC M2 I/O33, GCK3 I/O34 (HDC/TDI) I/O35 I/O36 I/O37 Not a User I/O I/O38 (LDC/TDO) I/O39 I/O40 Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 ...
Page 186
Table 7-3. AT94K05 96 FPGA I/O GND I/O41 I/O42 I/O43/TMS I/O44/TCK I/O45 I/O46 I/O47 (TD7) I/O48 (InitErr) VDD Notes: AT94KAL Series FPSLIC 186 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O I/O59 I/O117 I/O60 I/O118 I/O119 ...
Page 187
Table 7-3. AT94K05 96 FPGA I/O GND I/O49 (TD6) I/O50 (TD5) I/O51 I/O52 I/O53 (TD4) I/O54 (TD3) I/O55 I/O56 GND Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O GND GND I/O73 (TD6) I/O145 (TD6) ...
Page 188
Table 7-3. AT94K05 96 FPGA I/O I/O57 I/O58 I/O59 (TD2) I/O60 (TD1) I/O61 I/O62 I/O63 (TD0) I/O64, GCK4 GND CON VCC RESET PE0 PE1 PD0 PD1 Notes: AT94KAL Series FPSLIC 188 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O ...
Page 189
Table 7-3. AT94K05 96 FPGA I/O PE2 PD2 No Connect PD3 PD4 PE3 CS0, Cs0n SDA SCL PD5 PD6 PE4 PE5 VDD GND PE6 PE7 (CHECK) PD7 INTP0 XTAL1 XTAL2 RX0 Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 ...
Page 190
Table 7-3. AT94K05 96 FPGA I/O TX0 GND INTP1 INTP2 TOSC1 TOSC2 RX1 TX1 D0 INTP3 (CSOUT) CCLK VCC I/O65:95 Are Unbonded Testclock GND I/O97 (A0) I/O98, GCK7 (A1) I/O99 I/O100 I/O101 (CS1, A2) I/O102 (A3) Notes: AT94KAL Series FPSLIC ...
Page 191
Table 7-3. AT94K05 96 FPGA I/O I/O104 I/O103 GND I/O105 I/O106 I/O107 (A4) I/O108 (A5) Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O (1) VCC GND I/O151 I/O301 I/O152 I/O302 I/O153 I/O303 I/O154 I/O304 ...
Page 192
Table 7-3. AT94K05 96 FPGA I/O I/O109 I/O110 I/O111 (A6) I/O112 (A7) GND VDD I/O113 (A8) I/O114 (A9) I/O115 I/O116 I/O117 (A10) I/O118 (A11) Notes: AT94KAL Series FPSLIC 192 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA ...
Page 193
Table 7-3. AT94K05 96 FPGA I/O I/O119 I/O120 GND I/O121 I/O122 I/O123 (A12) I/O124 (A13) I/O125 I/O126 Notes: 1138I–FPSLI–1/08 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O GND I/O355 I/O356 (2) (2) VDD VDD I/O177 I/O357 ...
Page 194
Table 7-3. AT94K05 96 FPGA I/O I/O127 (A14) I/O128, GCK8 (A15) VCC Notes: AT94KAL Series FPSLIC 194 AT94K Pin List (Continued) AT94K10 AT94K40 192 FPGA I/O 384 FPGA I/O I/O191 (A14) I/O383 (A14) I/O192, GCK8 I/O384, GCK8 (A15) (A15) (1) ...
Page 195
... Low Profile Plastic Gull Wing Quad Flat Package (LQFP) 208Q1 208-lead, Plastic Gull Wing Quad Flat Package (PQFP) 1138I–FPSLI–1/08 AT94KAL Series FPSLIC Ordering Code AT94K10AL-25AJC Ordering Code AT94K05AL-25AQU AT94K05AL-25BQU AT94K10AL-25BQU AT94K10AL-25DQU AT94K40AL-25BQU AT94K40AL-25DQU Package Type Package Operation Range Commercial 84J (0° 70° C) Package Operation Range ...
Page 196
Packaging Information 9.1 84J – PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is ...
Page 197
TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
Page 198
LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller ...
Page 199
PQFP e Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the ...
Page 200
Thermal Coefficient Table Package Style Lead Count PLCC TQFP LQFP PQFP 11. Revision History Revision Level – Release Date History 1. Updated Ordering Codes. I – January 2008 2. Removed references to ATFS Series Configurators. 3. Changed maximum oscillator ...