5962-8867004LA Cypress Semiconductor Corp, 5962-8867004LA Datasheet

5962-8867004LA

Manufacturer Part Number

5962-8867004LA

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.5962-8867004LA.pdf (12 pages)

Specifications of 5962-8867004LA

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Features

100% programming and functional testing

Functional Description

The Cypress PALC22V10D is a CMOS Flash Erasable sec-

ond-generation programmable array logic device. It is imple-

mented with the familiar sum-of-products (AND-OR) logic

structure and the programmable macrocell.

The PALC22V10D is executed in a 24-pin 300-mil molded DIP ,

a 300-mil cerDIP , a 28-lead square ceramic leadless chip car-

rier, a 28-lead square plastic leaded chip carrier, and provides

up to 22 inputs and 10 outputs. The 22V10D can be electrically

Cypress Semiconductor Corporation

• Advanced second-generation PAL architecture

• Low power

• CMOS Flash EPROM technology for electrical erasabil-

• Variable product terms

• User-programmable macrocell

• Up to 22 input terms and 10 outputs

• DIP, LCC, and PLCC available

• High reliability

ity and reprogrammability

— 90 mA max. commercial (10 ns)

— 130 mA max. commercial (7.5 ns)

— 2 x(8 through 16) product terms

— Output polarity control

— Individually selectable for registered or combinato-

— 7.5 ns commercial version

— 10 ns military and industrial versions

— 15-ns commercial and military

— 25-ns commercial and military

— Proven Flash EPROM technology

rial operation

5 ns t

7.5 ns t

133-MHz state machine

6 ns t

10 ns t

110-MHz state machine

versions

Flash Erasable, Reprogrammable CMOS PAL® Device

•

3901 North First Street

For new designs, please refer to the PALCE22V10

erased and reprogrammed. The programmable macrocell pro-

vides the capability of defining the architecture of each output

individually. Each of the 10 potential outputs may be specified

as “registered” or “combinatorial.” Polarity of each output may

also be individually selected, allowing complete flexibility of

output configuration. Further configurability is provided

through “array” configurable “output enable” for each potential

output. This feature allows the 10 outputs to be reconfigured

as inputs on an individual basis, or alternately used as a com-

bination I/O controlled by the programmable array.

PALC22V10D features a variable product term architecture.

There are 5 pairs of product term sums beginning at 8 product

terms per output and incrementing by 2 to 16 product terms

per output. By providing this variable structure, the PAL C

22V10D is optimized to the configurations found in a majority

of applications without creating devices that burden the prod-

uct term structures with unusable product terms and lower per-

formance.

Additional features of the Cypress PALC22V10D include a

synchronous preset and an asynchronous reset product term.

These product terms are common to all macrocells, eliminat-

ing the need to dedicate standard product terms for initializa-

tion functions. The device automatically resets upon power-up.

The PALC22V10D, featuring programmable macrocells and

variable product terms, provides a device with the flexibility to

implement logic functions in the 500- to 800-gate-array com-

plexity. Since each of the 10 output pins may be individually

configured as inputs on a temporary or permanent basis, func-

tions requiring up to 21 inputs and only a single output and

down to 12 inputs and 10 outputs are possible. The 10 poten-

tial outputs are enabled using product terms. Any output pin

may be permanently selected as an output or arbitrarily en-

abled as an output and an input through the selective use of

individual product terms associated with each output. Each of

these outputs is achieved through an individual programmable

macrocell. These macrocells are programmable to provide a

combinatorial or registered inverting or non-inverting output. In

a registered mode of operation, the output of the register is fed

back into the array, providing current status information to the

array. This information is available for establishing the next re-

sult in applications such as control state machines. In a com-

binatorial configuration, the combinatorial output or, if the out-

put is disabled, the signal present on the I/O pin is made

available to the array. The flexibility provided by both program-

mable product term control of the outputs and variable product

terms allows a significant gain in functional density through the

use of programmable logic.

Along with this increase in functional density, the Cypress

PALC22V10D provides lower-power operation through the use

of CMOS technology, and increased testability with Flash re-

programmability.

PAL is a registered trademark of Advanced Micro Devices

•

San Jose

•

July 1991 - Revised October 1995

CA 95134

PALC22V10D

•

408-943-2600

Related parts for 5962-8867004LA

5962-8867004LA Summary of contents

Page 1

... The 22V10D can be electrically Cypress Semiconductor Corporation For new designs, please refer to the PALCE22V10 erased and reprogrammed. The programmable macrocell pro- vides the capability of defining the architecture of each output individually ...

Page 2

Logic Block Diagram (PDIP/CDIP Reset Macrocell Macrocell Macrocell I/O 9 I/O 8 I/O 7 Pin Configuration ...

Page 3

Macrocell FEEDBACK Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential (Pin 24 to Pin 12) DC ...

Page 4

Electrical Characteristics Over the Operating Range Parameter Description I Standby Power Supply CC1 Current [6] I Operating Power Supply CC2 Current Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute ...

Page 5

Load Speed C Package L 7.5, 10, 15 PDIP , CDIP, ns PLCC, LCC Parameter V Output W aveform Measurement Level 0.5V t 2.6V 0.5V ER (+) V OL ...

Page 6

Commercial Switching Characteristics PALC22V10D Parameter Description t Input to Output PD [8, 9] Propagation Delay t Input to Output Enable Delay EA t Input to Output Disable Delay ER [ Clock to Output Delay CO t Input or ...

Page 7

Military and Industrial Switching Characteristics PALC22V10D Parameter Description t Input to Output PD Propagation Delay t Input to Output Enable Delay EA t Input to Output Disable Delay ER t Clock to Output Delay CO t Input or Feedback Set-Up ...

Page 8

Switching Waveform INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET ASYNCHRONOUS RESET REGISTERED OUTPUTS COMBINATORIAL OUTPUTS [16] Power-Up Reset Waveform 10% POWER SUPPLY VOLTAGE REGISTERED ACTIVE L OW OUTPUTS CLOCK SPR ...

Page 9

Functional Logic Diagram for PALC22V10D ...

Page 10

Ordering Information (mA) (ns) (ns) (ns) Ordering Code 130 7 PALC22V10D-7JC PALC22V10D-7PC PALC22V10D-10JC PALC22V10D-10PC 150 PALC22V10D-10JI PALC22V10D-10PI 150 PALC22V10D-10DMB PALC22V10D-10KMB ...

Page 11

Package Diagrams 24–Lead (300–Mil) CerDIP D14 MIL-STD-1835 D-9 Config. A 24–Lead Rectangular Cerpack K73 MIL-STD-1835 F-6 Config. A 28–Lead Plastic Leaded Chip Carrier J64 28–Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 11 PALC22V10D ...

Page 12

... Package Diagrams (continued) © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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