PALCE20V8-15JC Cypress Semiconductor Corp, PALCE20V8-15JC Datasheet - Page 5

PALCE20V8-15JC

Manufacturer Part Number
PALCE20V8-15JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of PALCE20V8-15JC

Family Name
Pal®
Process Technology
EECMOS
# Macrocells
8
# I/os (max)
8
Frequency (max)
62.5MHz
Propagation Delay Time
15ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
28
Supply Current
90mA
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PALCE20V8-15JC
Manufacturer:
CY
Quantity:
264
Part Number:
PALCE20V8-15JC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-03026 Rev. *B
AC Test Loads and Waveforms
Commercial and Industrial Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
Shaded areas contain preliminary information.
Notes:
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
PD
PZX
PXZ
PD
PZX
PXZ
EA
ER
CO
S
H
P
Parameter
9. Min. times are tested initially and after any design or process changes that may affect these parameters.
, t
level has fallen to 0.5 volts below V
Specification
, t
, t
CO
EA
ER
Input to Output
Propagation Delay
OE to Output Enable
OE to Output Disable
Input to Output Enable
Delay
Input to Output
Disable Delay
Clock to Output Delay
Input or Feedback Set-up
Time
Input Hold Time
External Clock Period
(t
CO
+ t
[8]
S
)
Description
Closed
Z ⎜ H: Open
Z ⎜ L: Closed
H ⎜ Z: Open
L ⎜ Z: Closed
OH
[8,10]
min. or a previous LOW level has risen to 0.5 volts above V
S
[9]
1
GND
3.0V
[9]
OUTPUT
2 ns
USE ULTRA37000
MAX
Min.
ALL NEW DESIGNS
1
1
3
0
7
50 pF
20V8−5
5 pF
internal (1/f
C
L
10%
Max.
5V
90%
ALL INPUT PULSES
5
5
5
6
6
4
MAX3
S1
R1
R2
200Ω
) as measured (see Note 7 above) minus t
R
Commercial
Min.
1
12
1
1
7
0
20V8−7
C
L
Max.
7.5
390Ω
[3]
6
6
9
9
5
R
OL
TM
2
TEST POINT
max.
FOR
Min.
10
17
90%
20V8−10
1
1
0
10%
390Ω
≤ 2 ns
R
Max.
1
10
10
10
10
10
Military
7
S
.
Min.
750Ω
12
22
20V8−15
1
1
0
R
2
Max.
15
15
15
15
15
10
Measured Output Value
H ⎜ Z: V
PALCE20V8
L ⎜ Z: V
Min.
15
27
20V8−25
1
1
0
1.5V
1.5V
OL
OH
Page 5 of 14
Max.
25
20
20
25
25
12
+ 0.5V
− 0.5V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback

Related parts for PALCE20V8-15JC