PALCE20V8-15PC Cypress Semiconductor Corp, PALCE20V8-15PC Datasheet
PALCE20V8-15PC
Specifications of PALCE20V8-15PC
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PALCE20V8-15PC Summary of contents
Page 1
... The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically- erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user’s design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming fi ...
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... I/O I FUNCTIONAL DESCRIPTION The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC -MC ). Each macrocell can be configured as a registered output, combinatorial output combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable (OE) for all fl ...
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... This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices ...
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... SG0 replaces SG1 on the feedback multiplexer. 7 These configurations are summarized in Table 1 and illustrated in Figure 2. If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. ...
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... Only seven product terms are available x Table 1. Macrocell Configuration Devices Emulated SG0 SG1 SL0 X Device Uses No Registers PAL20R8, 20R6 20R4 PAL20R6, 20R4 PALCE20V8 Family Cell Devices Configuration Emulated Combinatorial PAL20L2, 18L4, 0 Output 16L6, 14L8 1 Input PAL20L2, 18L4, 16L6 Combinatorial 1 PAL20L8 I/O 5 ...
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... This macrocell configuration is not available on pins 18 (21) and 19 (23 Registered active high d. Combinatorial I/O active high Note 1 f. Combinatorial output active high g. Dedicated input Figure 2. Macrocell Configurations PALCE20V8 Family CLK V CC Note 1 Note 2 Adjacent I/O Pin 16491E ...
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... Security Bit A security bit is provided on the PALCE20V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. ...
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... LOGIC DIAGRAM CLK ( ( ( ( ( ( SG0 SG1 SG1 SG1 SG1 PALCE20V8 Family (28 (27 SL0 I (26 SG0 SL0 SL0 I (25 SG1 SL0 SL0 I (24 SG1 SL0 SL0 I (23 SG1 SL0 4 CLK OE 16491E ...
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... LOGIC DIAGRAM (CONTINUED ( (10 (11 (12 (13 SG1 SG1 SG1 SG1 0 1 SG0 PALCE20V8 Family CLK SL0 I (21 SG1 SL0 SL0 I (20 SG1 SL0 SL0 I (19 SL0 1 SG1 SL0 I (18 SL0 0 SG0 (17) 13 OE/I 11 (16) 16491E-4 (concluded) 9 ...
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... Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), V OUT V = Max CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-5/7/10 (Com’l) ) Operating Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 = 125 115 Unit µA µA µ ...
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... Max 1/( 142 1/( (Note 5) 166 S CF 1/( 166 and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE20V8H-5/7/10 (Com’l) Typ Unit 5 pF ° 5 MHz - Min Max Min Max Unit 100 66 ...
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... Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz (Note 4) CC and I (or I and I ). OZL IH OZH vs. frequency graph for typical measurements. CC PALCE20V8Q-10 (Com’ Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 55 Unit µA µA µA µ ...
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... 2 OUT = 2.0 V Parameter Description 1/( 1/( (Note 4) CNT S CF 1/( and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE20V8Q-10 (Com’l) Typ Unit 5 pF ° 5 MHz 8 pF -10 2 Min Max Unit 7 7 66.7 MHz 71 ...
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... Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-15/25 Q-15/25 (Com’l) ) Operating Min Max = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 Unit µA µA µA µ ...
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... 1/f (internal feedback) – MAX S Test Conditions 2 OUT = 2.0 V 1/( 1/( (Note 3) CNT S CF 1/( can be found using the following equation: CF PALCE20V8H-15/25 Q-15/25 (Com’l) Typ Unit 5 pF ° 5 MHz 8 pF -15 -25 Min Max Min Max Unit ...
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... Max (Note 5 Max , OUT Max , OUT 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-15/25 Q-20/25 (ind) ) Operating Min Max Unit 2.4 0.5 2.0 0.8 10 –100 (Note (Note 2) –100 IL –30 –150 H 130 µA µA µA µ ...
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... CF MAX S Test Conditions 2 5 MHz V OUT = 2.0 V -15 Min Max 1/( 45 1/( (Note 1/( 62 can be found using the following equation: CF PALCE20V8H-15/25 Q-20/25 (ind) Typ Unit 5 pF ° -20 -25 Min Max Min Max Unit 41.6 37 MHz 45.4 40 MHz 50.0 41.6 ...
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... Output Notes 1 Input pulse amplitude 3 Input rise and fall times typical. 18 Input or Feedback Clock V T Registered Output 16491E-5 Input V T Output t WL 16491E-7 d. Input to output disable/enable PXZ V – output disable/enable PALCE20V8 Family 16491E-6 b. Registered output – 0. 0.5V OL 16491E-8 t PZX V T 16491E-9 ...
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... May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State KS000010-PAL Commercial 390 200 5 pF H-5: 200 PALCE20V8 Family 16491E-10 R Measured Output Value 2 1 – ...
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... By utilizing 50% of the device, a midpoint is defined for I estimate the I requirements for a particular design Frequency (MHz) I vs. Frequency CC . From this midpoint, a designer may scale the I CC PALCE20V8 Family 20V8H-5 20V8H-7 20V8H-10 20V8H-15/25 20V8Q-15/25 50 16491E-11 graphs up or down to CC ...
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... N Max Reprogramming Cycles ROBUSTNESS FEATURES The PALCE20V8X-X/5 have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise fi ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE20V8H-7 AND PALCE20V8H > ESD Protection and Clamping Device Rev Letter PALCE20V8H-7 A PALCE20V8H Programming Programming Pins only Voltage Detection Typical Input > Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE20V8 Family Positive Programming Overshoot Circuitry Filter Feedback ...
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... Feedback Input I/O Topside Marking: Lattice/Vantis CMOS PLDs are marked on top of the package in the following manner: PALCEXXX Datecode (3 numbers) Lot ID (4 characters)––(Rev Letter) The Lot ID and Rev Letter are separated by two spaces. PALCE20V8 Family 100 k 0.5 k 16491E-13 23 ...
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... POWER-UP RESET The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below ...
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... Therefore, the measurements can only be used in a similar environment. PDID 19 73 200 lfpm air 61 400 lfpm air 53 600 lfpm air 50 800 lfpm air 47 measurement relative to a specific location on the pack- jc PALCE20V8 Family Typ PLCC Unit 19 C/W 55 C/W 45 C/W 41 C/W 38 C/W ...
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... Top View SKINNYDIP CLK GND 12 13 Note: Pin 1 is marked for orientation. PIN DESIGNATIONS CLK = Clock NC GND = Ground Input V CC I/O = Input/Output OE/I 11 16491E- Connect = Output Enable = Supply Voltage PALCE20V8 Family PLCC GND I/O 1 16491E-17 ...
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... C I PACKAGE TYPE P J Valid Combinations PC, JC, PI, JI PC PC, JC, PI, JI Valid Combinations PALCE20V8 Family /4 = First Revision /5 = Second Revision (Same Algorithm as /4) ° ° = Commercial ( + Industrial (-40 ° +85 ° 24-Pin 300 mil Plastic SKINNY DIP (PD3024) = 28-Pin Plastic Leaded Chip ...