PALCE20V8-15PC Cypress Semiconductor Corp, PALCE20V8-15PC Datasheet - Page 2

• Manufacturer Part Number: PALCE20V8-15PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of PALCE20V8-15PC

• Lead Free Status / RoHS Status: Not Compliant

The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells
(MC
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to V
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed
2
OE
/I
11
Input
Mux.
0
-MC
I
12
7
MACRO
). Each macrocell can be configured as a registered output, combinatorial output,
MC
I/O
0
0
MACRO
MC
I/O
1
1
MACRO
MC
I/O
2
2
Programmable AND Array
PALCE20V8 Family
MACRO
MC
I/O
3
10
3
I 1 – I 10
40 x 64
CC
MACRO
MC
or GND. Product terms with all bits
I/O
4
4
MACRO
MC
I/O
5
5
MACRO
MC
6
I/O
6
MACRO
MC
I/O
7
7
Input
Mux.
16491E
I
13
CLK/I
0