5962-89841033A Cypress Semiconductor Corp, 5962-89841033A Datasheet - Page 7

• Manufacturer Part Number: 5962-89841033A
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-89841033A

• Process Technology: CMOS
• # Macrocells: 10
• # I/os (max): 10
• Frequency (max): 83.3MHz
• Propagation Delay Time: 15ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 28
• Supply Current: 130mA
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03027 Rev. *C
Commercial Switching Characteristics PALCE22V10
Military and Industrial Switching Characteristics PALCE22V10
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
Notes:
Parameter
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
S1
S2
H
P
WH
WL
MAX1
MAX2
MAX3
CF
AW
AR
AP
SPR
PR
PD
EA
ER
CO
S1
S2
H
P
WH
WL
MAX1
MAX2
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in V
Parameter
Input or Feedback Set-Up Time
Synchronous Preset Set-Up
Time
Input Hold Time
External Clock Period (t
Clock Width HIGH
Clock Width LOW
External Maximum
Frequency (1/(t
Data Path Maximum Frequency
(1/(t
Internal Feedback Maximum
Frequency (1/(t
Register Clock to
Feedback Input
Asynchronous Reset Width
Asynchronous Reset
Recovery Time
Asynchronous Reset to
Registered Output Delay
Synchronous Preset
Recovery Time
Power-up Reset Time
WH
+ t
Input to Output
Propagation Delay
Input to Output Enable Delay
Input to Output Disable Delay
Clock to Output Delay
Input or Feedback Set-up Time
Synchronous Preset Set-up Time
Input Hold Time
External Clock Period (t
Clock Width HIGH
Clock Width LOW
External Maximum Frequency
(1/(t
Data Path Maximum Frequency
(1/(t
CC
WL
Description
must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
CO
WH
))
[6, 12]
+ t
CO
CF
+ t
[6,14]
S
USE ULTRA37000
ALL NEW DESIGNS
WL
[6]
+ t
[6]
Description
+ t
))
[11]
S
))
S
))
[6, 12 ]
))
[6,15]
[6,13]
[11]
CO
[6]
[6]
[8]
+ t
S
[8]
)
CO
MAX
Min.
+ t
143
200
181
2.5
2.5
internal (1/f
22V10-5
3
4
0
7
8
4
4
1
[9]
S
[10]
)
Max.
2.5
7.5
TM
MAX3
Min.
76.9
142
12
3
2
6
7
0
3
3
FOR
22V10-10
) as measured (see Note above) minus t
Min.
100
166
133
10
22V10-7
5
6
0
3
3
8
5
6
1
Max.
10
10
10
7
Max.
(continued)
2.5
12
Min.
76.9
142
111
Min.
50.0
83.3
22V10-10
12
10
6
7
0
3
3
6
8
1
10
10
20
3
2
0
6
6
[2, 7]
22V10-15
[2, 7]
Max.
13
3
Max.
S
15
15
15
.
8
Min.
55.5
83.3
68.9
22V10-15
10
10
20
15
10
10
0
6
6
1
Min.
30.3
35.7
Max.
18
18
33
14
14
4.5
20
3
2
0
22V10-25
PALCE22V10
Min.
33.3
35.7
38.5
22V10-25
15
15
30
13
13
25
25
15
0
1
Max.
25
25
25
15
Max.
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13
25
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs