MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 13

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Output Data Timing
Figure 8:
LV and FV
LV Format Options
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
D
OUT
PIXCLK
[11:0]
FV
LV
Default Pixel Output Timing
Vertical Blanking Horiz Blanking
The output images are divided into frames, which are further divided into lines. By
default, the sensor produces 1944 rows of 2592 columns each. The FV and LV signals
indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a
clock to latch the data. For each PIXCLK cycle, one 12-bit pixel datum outputs on the
D
occur when FV is negated are called vertical blanking. PIXCLK cycles that occur when
only LV is negated are called horizontal blanking.
The timing of the FV and LV outputs is closely related to the row time and the frame time.
FV will be asserted for an integral number of row times, which will normally be equal to
the height of the output image. If Show_Dark_Rows is set, the dark sample rows will be
output before the active image, and FV will be extended to include them. In this case,
FV’s leading edge happens at time 0.
LV will be asserted during the valid pixels of each row. The leading edge of LV will be
offset from the leading edge of FV by 609 PIXCLKs. If Show_Dark_Columns is set, the
dark columns will be output before the image pixels, and LV will be extended back to
include them; in this case, the first pixel of the active image still occurs at the same posi-
tion relative to the leading edge of FV. Normally, LV will only be asserted if FV is asserted;
this is configurable as described below.
The default situation is for LV to be negated when FV is negated. The other option avail-
able is shown in Figure 9 on page 14. If Continuous_LV is set, LV is asserted even when
FV is not, with the same period and duty cycle. If XOR_Line_Valid is set, but not
Continuous_Line_Valid, the resulting LV will be the XOR of FV and the continuous LV.
OUT
pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that
Valid Image Data
P0
P1
13
P2
P3
MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
P4
Horiz Blanking Vertical Blanking
Pn
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
Output Data Timing