MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 28

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 13:
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
Reg. #
R0x010
R0x011
R0x012
R16:0
R17:0
R18:0
Bits
14:13
15:13
15:0
12:9
15:0
15:8
15:0
12:8
Register Description (continued)
7:4
3:2
7:6
5:0
7:5
4:0
15
8
1
0
Default
0x0050
0x0000
0x0000
0x0000
0x0005
0x0000
0x0000
0x6404
0x0064
0x0004
0x0000
0x0000
0x0000
X
X
X
X
X
Name
PLL Control (RW)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Use PLL
When set, use the PLL output as the system clock. When clear, use EXTCLK as the system clock.
Power PLL
When set, the PLL is powered. When clear, it is not powered.
PLL Config 1 (RW)
PLL m Factor
PLL output frequency multiplier.
Legal values: [16, 255].
Reserved
PLL n Divider
PLL output frequency divider minus 1.
Legal values: [0, 63].
PLL Config 2 (RW)
Reserved
Reserved
Reserved
PLL p1 Divider
PLL system clock divider minus 1. Use odd numbers. If this is set to an even number, the system clock
duty cycle will not be 50:50. In this case, set all bits in R101 or slow down EXTCLK.
Legal values: [0, 127].
28
MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
Registers