UPD3747D Renesas Electronics America, UPD3747D Datasheet
UPD3747D
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UPD3747D Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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PIXELS CCD LINEAR IMAGE SENSOR μ The PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. μ The PD3747 is a 2-output type CCD sensor with 2 ...
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BLOCK DIAGRAM φ CP GND GND (Even) 22 OUT V 1 (Odd) 1 OUT φ CCD analog shift register Transfer gate Photocell · · · Transfer gate CCD analog ...
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PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) μ • PD3747D-A Output signal 1 (Odd) V OUT Output drain voltage V No connection NC φ Reset gate clock φ Last stage shift register ...
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ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Note Operating ambient temperature Storage temperature Note Use at the condition without dew condensation. ...
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ELECTRICAL CHARACTERISTICS T = +25° φ MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = light source : 3200 K halogen lamp ...
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INPUT PIN CAPACITANCE (T = +25° Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance ...
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Data Sheet S14892EJ4V0DS μ PD3747 36 34 ...
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TIMING CHART 2 (Bit clamp mode) t1 90% φ 1 10% 90% φ 2 10% t1' 90% φ 90% φ t10 90% φ OUT ...
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TIMING CHART 3 (Line clamp mode) t1 90% φ 1 10% 90% φ 2 10% t1' 90% φ 90% φ R 10% φ CP "L" OUT Symbol t1, t2 t1’, t2’ t3 ...
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TIMING CHART 4 (Bit clamp mode, Line clamp mode) 90% φ TG 10% t16 90% φ 1 φ φ φ R φ CP φ φ Note Set the R and CP to low level during this period. Symbol ...
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DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...
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Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum ...
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Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels ∑ – ...
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STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature (without infrared cut filter and heat absorbing filter) (T 100 ...
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APPLICATION CIRCUIT EXAMPLE + μ μ 10 F/ μ 47 μ F/ Ω φ Ω φ Ω φ Ω φ 2 Caution ...
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PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400)) (Unit : mm) The 1st valid pixel 1 ± 0.3 3.2 42.2 ± 0.25 48.6 ± 0.5 1.02 ± 0.15 2.54 0.46 ± 0.06 25.4 16 1.60±0.25 ...
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RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...
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NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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The information in this document is current as of October, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most ...