MC100EPT23D ON Semiconductor, MC100EPT23D Datasheet

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MC100EPT23D

Manufacturer Part Number
MC100EPT23D
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100EPT23D

Logic Family
ECL
Logical Function
Translator
Technology
ECL
High Level Output Current
-3mA
Low Level Output Current
24mA
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC N
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Abs. Propagation Delay Time
2.4ns
Mounting
Surface Mount
Pin Count
8
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant

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MC100EPT23
3.3V Dual Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8-lead SOIC package and the dual gate design of the EPT23
makes it ideal for applications which require the translation of a clock
or data signal.
are no LVPECL outputs or an external V
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL/LVDS input referenced from a V
Features
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 18
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to
The EPT23 is available in only the ECL 100K standard. Since there
1.5 ns Typical Propagation Delay
Maximum Operating Frequency > 275 MHz
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
24 mA LVTTL Outputs
Operating Range: V
Pb−Free Packages are Available
CC
= 3.0 V to 3.6 V with GND = 0 V
BB
reference, the EPT23 does
CC
of +3.3 V.
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
8
*For additional marking information, refer to
8
1
(Note: Microdot may be in either location)
Application Note AND8002/D.
1
1
ORDERING INFORMATION
A
L
Y
W
M
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
CASE 506AA
CASE 948R
MN SUFFIX
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
SOIC−8
DFN8
Publication Order Number:
DIAGRAMS*
MC100EPT23/D
8
1
MARKING
8
1
ALYWG
1
KPT23
ALYW
KA23
G
G
4

Related parts for MC100EPT23D

MC100EPT23D Summary of contents

Page 1

MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. ...

Page 2

LVPECL LVTTL (Top View) Figure 1. Logic Diagram and 8−Lead Pinout Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note ...

Page 3

Table 4. PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current (Outputs set to HIGH) CCH I Power Supply Current (Outputs set to LOW) CCL V Input HIGH Voltage IH V Input LOW Voltage IL V Input HIGH Voltage Common ...

Page 4

2.0 JITTER 1.0 0.0 0 100 200 FREQUENCY (MHz) Figure 2. Typical V / Jitter versus Frequency (255C) OH APPLICATION CHARACTERISTIC TEST includes L fixture capacitance GND Figure 3. TTL ...

Page 5

... ORDERING INFORMATION Device MC100EPT23D MC100EPT23DG MC100EPT23DR2 MC100EPT23DR2G MC100EPT23DT MC100EPT23DTG MC100EPT23DTR2 MC100EPT23DTR2G MC100EPT23MNR4 MC100EPT23MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... NOTE 3 0.05 C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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