SR1530HCLR Intel (CPU), SR1530HCLR Datasheet - Page 52

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SR1530HCLR

Manufacturer Part Number
SR1530HCLR
Description
Manufacturer
Intel (CPU)
Datasheet

Specifications of SR1530HCLR

Lead Free Status / RoHS Status
Not Compliant
T
T
T
T
T
T
T
T
T
T
T
sb_on_delay
vout_holdup
pwok_holdup
pson_on_delay
pwok_on
pwok_low
sb_vout
5VSB_holdup
Power and Environmental Specifications
42
ac_on_delay
pson_pwok
pwok_off
Item
V out
V1
V2
V3
V4
Delay from AC being applied to 5VSB being within regulation.
Delay from AC being applied to all output voltages being
within regulation.
Time all output voltages stay within regulation after loss of
AC. Measured at 75% of maximum load.
Delay from loss of AC to de-assertion of PWOK. Measured at
75% of maximum load.
Delay from PSOn
limits.
Delay from PSOn
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSOn signal.
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
Time the 5VSB output voltage stays within regulation after
loss of AC.
10% V out
#
#
active to output voltages within regulation
deactive to PWOK being de-asserted.
Figure 12. Output Voltage Timing
Description
Intel order number: D64569-006
T vout_rise
T vout_on
Table 38. Turn On/Off Timing
Intel
T vout_off
21
20
5
100
1
100
50
70
Minimum
®
Server Board S5000VCL TPS
1500
2500
400
50
500
1000
Maximum
AF001023
Revision 2.2
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
Units