AD5255BRU250-RL7 Analog Devices Inc, AD5255BRU250-RL7 Datasheet - Page 5

• Manufacturer Part Number: AD5255BRU250-RL7
• Manufacturer: Analog Devices Inc

Specifications of AD5255BRU250-RL7

• Number Of Elements: 3
• Resistance (max): 250KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.2V
• Dual Supply Voltage (max): ±2.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

Single supply: V
Dual supply: V
Table 2.
Parameter
DYNAMIC CHARACTERISTICS
INTERFACE TIMING CHARACTERISTICS
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
6
7
Typical represents average readings at 25°C, V
Guaranteed by design and not subject to production test.
All dynamic characteristics use V
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
See the timing diagram for location of measured values.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
derates with junction temperature.
Bandwidth −3 dB
Total Harmonic Distortion
V
Resistor Noise Spectral Density
Digital Crosstalk
Analog Crosstalk
(APPLY TO ALL PARTS)
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
EEMEM Data Storing Time
EEMEM Data Restoring Time
EEMEM Data Restoring Time
EEMEM Data Rewritable Time
Endurance
Data Retention
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
W
Fall Time of Both SDA and SCL
Rise Time of Both SDA and SCL
and Start
Start Condition
Start Condition
Signals
Signals
at Power-On
on Restore Command or
Reset Operation
Settling Time
Bus Free Time Between Stop
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for Repeated
Setup Time for Stop Condition
Hold Time (Repeated)
Data Setup Time
Data Hold Time
6
DD
DD
7
= 2.25 V or 2.75 V, V
= 3 V to 5.5 V and −40°C < T
4, 5
DD
2, 3
= 5 V.
SS
DD
= −2.25 V or −2.75 V, and −40°C < T
= 5 V.
Symbol
BW
THD
t
e
C
C
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
S
1
2
3
4
5
6
7
8
9
10
EEMEM_STORE
EEMEM_RESTORE1
EEMEM_RESTORE2
EEMEM_REWRITE
N_WB
T
AT
W
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
A
< +85°C, unless otherwise noted.
Rev. A | Page 5 of 20
Conditions
V
V
V
V
code 0x000 to 0x100, R
R
V
adjacent RDAC making full-scale change
Signal input at A0 and measure output at
W1, f = 1 kHz
After this period the first clock pulse is
generated
55°C
DD
A
A
W
AB
A
= 1 V rms, V
= V
= V
= 0.50% error band,
/V
= 25 kΩ/250 kΩ, T
SS
DD
DD
= ±2.5 V, R
, V
, V
B
B
= 0 V,
= 0 V, measure V
B
= 0 V, f = 1 kHz
A
AB
< + 85°C, unless otherwise noted.
= 25 kΩ/250 kΩ
A
AB
= 25°C
= 25 kΩ/250 kΩ
W
with
Min
1.3
600
1.3
0.6
600
100
600
540
100
Typ
125/12
0.05
4/36
14/45
−80
−72
26
360
360
100
1
Max
400
50
900
300
300
AD5255
Unit
kHz
%
μs
nV√Hz
dB
dB
kHz
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
ms
μs
μs
μs
kcycles
years