K4S641632N-LI60000 Samsung Semiconductor, K4S641632N-LI60000 Datasheet - Page 10

• Manufacturer Part Number: K4S641632N-LI60000
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632N-LI60000

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 120mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

12.0 AC OPERATING TEST CONDITIONS
13.0 OPERATING AC PARAMETER
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
K4S641632N
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
6. t
(Fig. 1) DC output load circuit
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
and then rounding off to the next higher integer.
RC
870Ω
=t
RFC,
Parameter
Parameter
t
RDL
= t
WR
.
3.3V
1200Ω
30pF
CAS latency = 3
CAS latency = 2
V
V
OH
OL
(DC) = 0.4V, I
(DC) = 2.4V, I
t
t
t
t
t
t
t
t
t
RAS
Symbol
RRD
RCD
t
RAS
t
CCD
RDL
DAL
CDL
BDL
RP
RC
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
10 of 14
OL
OH
= 2mA
= -2mA
60
12
18
18
42
60
Industrial
2 CLK + tRP
See Fig. 2
tr/tf = 1/1
Version
2.4/0.4
Value
100
1.4
1.4
Output
2
1
1
1
2
1
(AC operating conditions unless otherwise noted)
75
15
20
20
45
65
(Fig. 2) AC output load circuit
Synchronous DRAM
Rev. 1.1 December 2007
(V
Z0 = 50Ω
DD
Unit
CLK
CLK
CLK
CLK
= 3.3V ± 0.3V, T
ea
ns
ns
ns
ns
us
ns
-
Vtt = 1.4V
Unit
50Ω
A
ns
30pF
V
V
V
Note
2,5,6
= 0 to 70°C)
1, 6
1
1
1
1
5
2
2
3
4