ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet
ADSP-BF592KCPZ
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ADSP-BF592KCPZ Summary of contents
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... DMA ACCESS BUS DCB DEB BOOT ROM Figure 1. Processor Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Blackfin Embedded Processor ADSP-BF592 2 S channels SPORT1 PORT F PPI TIMER2–0 GPIO UART SPI0 SPORT0 PORT G SPI1 TWI www ...
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... ADSP-BF592 TABLE OF CONTENTS Features ................................................................. 1 Memory ................................................................ 1 Peripherals ............................................................. 1 General Description ................................................. 3 Portable Low Power Architecture ............................. 3 System Integration ................................................ 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 5 Event Handling .................................................... 5 DMA Controllers .................................................. 6 Processor Peripherals ............................................. 6 Dynamic Power Management .................................. 8 Voltage Regulation ................................................ 9 Clock Signals ....................................................... 9 Booting Modes ................................................... 11 Instruction Set Description ................................... 12 Development Tools ............................................. 12 Designing an Emulator-Compatible Processor Board (Target) ...
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... GENERAL DESCRIPTION The ADSP-BF592 processor is a member of the Blackfin of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual- MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capa- bilities into a single instruction-set architecture ...
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... ADSP-BF592 The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering) and eight additional 32-bit pointer registers (for C-style indexed stack manipulation) ...
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... TMK (VDK core), C run-time libraries, and DSP libraries. See the VisualDSP++ documentation for more information. Custom ROM (Optional) The on-chip L1 Instruction ROM on the ADSP-BF592 may be customized to contain user code with the following features: • 64K bytes of L1 Instruction ROM available for custom code Figure 3. • ...
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... The inputs into the SIC and the default mappings into the CEC are described in the ADSP-BF59x Black- fin Processor Hardware Reference, “System Interrupts” chapter. The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers ...
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... SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. UART Port The ADSP-BF592 processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous trans- fers of serial data ...
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... DMA access is available to appropriately configured L1 memories. For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF59x Blackfin Pro- cessor Hardware Reference. Sleep Operating Mode—High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK) ...
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... T is the duration running at f RED VOLTAGE REGULATION The ADSP-BF592 processor requires an external voltage regula- tor to power the V consumption, the external voltage regulator can be signaled through EXT_WAKE to remove power from the processor core. This signal is high-true for power-up and may be connected directly to the low-true shut-down input of many common regulators ...
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... Figure 4. A design procedure for third-overtone oper- ation is discussed in detail in (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices web- site (www.analog.com)—use site search on “EE-168.” The Blackfin core runs at a different clock rate than the on-chip peripherals ...
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... PLL, clock frequencies, or serial bit rates. The boot ROM also features C-callable functions that can be called by the user application at run time. This enables second stage boot or boot management schemes to be implemented with ease. Rev Page August 2011 ADSP-BF592 ...
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... Blackfin processors also fully emulates the ADSP-BF592 processor. EZ-KIT Lite® Evaluation Board For evaluation of the ADSP-BF592 processor, use the EZ-KIT Lite boards soon to be available from Analog Devices. When these evaluation kits are available, order using part number ADZS-BF592-EZLITE ...
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... SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF592 processor are listed in Table 7. In order to maintain maximum function and reduce package size and pin count, some pins have dual, multiplexed functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics ...
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... ADSP-BF592 Table 7. Signal Descriptions (Continued) Signal Name PG11–GPIO/SPI1_SSEL5/PPI_D3 PG12–GPIO/SPI1_SSEL2/PPI_D4/WAKEN2 PG13–GPIO/SPI1_SSEL1/SPI1_SS/PPI_D5 PG14–GPIO/SPI1_SSEL4/PPI_D6/TACLK1 PG15–GPIO/SPI1_SSEL6/PPI_D7/TACLK2 TWI SCL SDA JTAG Port TCK TDO TDI TMS TRST EMU Clock CLKIN XTAL EXTCLK Mode Controls RESET NMI BMODE2–0 PPI_CLK External Regulator Control ...
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... J T Junction Temperature J 1 Bidirectional leads (PF15–0, PG15–0) and input leads (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF592 processor are 3.3 V tolerant (always accept up to 3.6 V maximum V ). Voltage compliance (on outputs Parameter value applies to all input and bidirectional leads, except SDA and SCL. ...
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... ADSP-BF592 ADSP-BF592 Clock Related Operating Conditions Table 8 describes the core clock timing requirements for the ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 10). Table 9 describes phase-locked loop operating conditions ...
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... Applies to bidirectional pins SCL and SDA. 5 Applies to all signal pins. 6 Guaranteed, but not tested. 7 See the ADSP-BF59x Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes. 8 See Table 11 for the list of I power vectors covered. DDINT ...
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... I DDINT DD-HIGH I DD-TYP ) and DDINT I DD-APP I DD-NOP I DD-IDLE 1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF592 processor. (mA) Voltage (V 1.25 V 1.30 V 1.13 1.29 2.01 2.16 3.2 3.5 4.86 5.3 7.73 8.36 11.37 12 ...
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... Table 15. is outside speci- DDEXT cur Table 16 Rev Page August 2011 ADSP-BF592 and V specifications have separate OH OL Electrical table. Groups DDEXT ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD ...
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... ADSP-BF592 PACKAGE INFORMATION The information presented in Figure 6 details about the package branding for the ADSP-BF592 proces- sor. For a complete listing of product availability, see Guide on Page 43. ADSP-BF592 tppZccc vvvvvv.x n.n #yyww country_of_origin Figure 6. Product Information on Package Table 17. Package Brand Information Brand Key ...
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... If the DF bit in the PLL_CTL register is set, the minimum f 5 Applies after power-up sequence is complete. See 6 The ADSP-BF592 processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF. t CKIN ...
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... ADSP-BF592 Table 19. Power-Up Reset Timing Parameter Timing Requirements t RESET Deasserted after the V RST_IN_PWR Specification CLKIN V DD_SUPPLIES , V , and CLKIN Pins are Stable and within DDINT DDEXT t RST_IN_PWR Figure 8. Power-Up Reset Timing Rev Page August 2011 Min Max 3500 × t CKIN Unit μs ...
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... PSUD Figure 9. PPI with External Frame Sync Timing DATA SAMPLED / FRAME SYNC SAMPLED t PCLKW t HFSPE t SDRPE Figure 10. PPI GP Rx Mode with External Frame Sync Timing Rev Page August 2011 ADSP-BF592 2.5 V/3.3 V DDEXT DDEXT Max Min Max t –1.5 SCLK –1.5 2 × ...
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... ADSP-BF592 PPI_CLK PPI_FS1/2 PPI_DATA FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 t SDRPE PPI_DATA FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA DATA DRIVEN / FRAME SYNC SAMPLED SFSPE HFSPE PCLKW t DDTPE t HDTPE Figure 11. PPI GP Tx Mode with External Frame Sync Timing DATA ...
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... SCLK 2 4 × t TSCLKE 2 4 × t RSCLKE Min 1 11.5 1 –1.5 1 11.5 1 –1 – –1.8 Rev Page August 2011 ADSP-BF592 V V DDEXT DDEXT 1.8V Nominal 2.5 V/3.3V Nominal Max Min Max 4.5 2 × t SCLK 4 × t TSCLKE 4 × t RSCLKE DDEXT DDEXT 1.8V Nominal 2 ...
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... ADSP-BF592 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW RSCLKx t DFSI t HOFSI RFSx (OUTPUT) t SFSI RFSx (INPUT) t SDRI DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW TSCLKx t D FSI t HOFSI TFSx (OUTPUT) t SFSI TFSx (INPUT) t DDTI t HDTI DTx ...
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... Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. TSCLKx DTx V 1.8V Nominal Min –2 1 DRIVE EDGE DRIVE EDGE t DTENE/I Figure 16. Serial Ports — Enable and Three-State Rev Page August 2011 ADSP-BF592 V DDEXT DDEXT 2.5 V/3.3V Nominal Max Min Max SCLK SCLK – SCLK ...
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... ADSP-BF592 Table 24. Serial Ports—External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFSx DDTLFSE or External RFSx in multi-channel mode with MFD = 0 t Data Enable from External RFSx in multi-channel mode with DTENLFSE 1, 2 MFD = 0 1 When in multi-channel mode, TFSx enable and TFSx valid follow external RFSx/TFSx setup to RSCLKx/TSCLKx > ...
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... DELAY TIME DATA TRANSMIT TFS/TMR (OUT) t DFTSCLKCNV TSCLKx (OUT) t DFTSCLKCNV TSCLKx (OUT) t DDTI t HDTI DTx Figure 18. Serial Ports Gated Clock Mode Rev Page August 2011 ADSP-BF592 V V DDEXT DDEXT 2.5 V/3.3 V Nominal Max Min Max 8 –1.8 – 3 0.5 × t – 3 TSCLK t – ...
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... ADSP-BF592 Serial Peripheral Interface (SPI) Port—Master Timing Table 26 and Figure 19 describe SPI port master operations. Table 26. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SCK Edge (Data Input Setup) SSPIDM t SCK Sampling Edge to Data Input Invalid ...
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... SPICHS t DDSPID t HDSPID t HSPID t t HDSPID DDSPID t SSPID Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing Rev Page August 2011 ADSP-BF592 V V DDEXT DDEXT 1.8V Nominal 2.5 V/3.3V Nominal Max Min Max – 1.5 2 × t – 1.5 SCLK – 1.5 2 × t – ...
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... ADSP-BF592 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF59x Hardware Reference Manual. General-Purpose Port Timing Table 28 and Figure 21 describe general-purpose port operations. Table 28. General-Purpose Port Timing Parameter Timing Requirement ...
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... SCLK t TOD t t TIS TIH Figure 22. Timer Cycle Timing Min Figure 23. Timer Clock Timing Rev Page August 2011 ADSP-BF592 V V DDEXT DDEXT 2.5 V/3.3V Nominal Max Min Max 1 × t SCLK 1 × t SCLK 8 – – 1) × – 1.5 (2 – ...
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... ADSP-BF592 JTAG Test And Emulation Port Timing Table 31 and Figure 24 describe JTAG port operations. Table 31. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 25 through Figure 33 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF592 processor. The curves represent the current drive capability of the output drivers. See Table 7 on Page 13 for information about which driver type corresponds to a particular pin. ...
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... ADSP-BF592 –10 –20 –30 –40 –50 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 30. Driver Type B Current (1.8V V 150 120 – 30 – 60 – 90 – 120 – 150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 31. Driver Type C Current (3.3V V 100 – 25 – 50 – 75 – 100 0 0 ...
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... the total leak Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Rev Page August 2011 ADSP-BF592 Figure 36). V )/2. DDEXT TESTER PIN ELECTRONICS 50: T1 45: 70 50: (impedance) 50 4.04 r 1.18 ns 0.5pF 2pF 400: Figure 36. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Figure 37 ...
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... ADSP-BF592 100 LOAD CAPACITANCE (pF) Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2. 100 LOAD CAPACITANCE (pF) Figure 39. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3. 100 LOAD CAPACITANCE (pF) Figure 40. Driver Type C Typical Rise and Fall Times (10%–90%) vs. ...
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... MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board Typical Unit 23.5 °C/W 20.9 °C/W 20.2 °C/W 11.2 °C/W 9.5 °C/W 0.21 °C/W 0.36 °C/W 0.43 °C/W can be used for a first ) P D Rev Page August 2011 ADSP-BF592 ...
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... ADSP-BF592 64-LEAD LFCSP LEAD ASSIGNMENT Table 33 lists the LFCSP leads by signal mnemonic. lists the LFCSP by lead number. Table 33. 64-Lead LFCSP Lead Assignment (Alphabetical by Signal) Signal Lead No. Signal BMODE0 29 PF7 BMODE1 28 PF8 BMODE2 27 PF9 EXTCLK/SCLK 57 PF10 CLKIN 61 PF11 EMU 19 PF12 EXT_WAKE 51 PF13 ...
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... LFCSP TOP VIEW PIN 16 PIN 17 PIN 32 Figure 43. 64-Lead LFCSP Lead Configuration (Top View) PIN 49 PIN 64 PIN 48 GND PAD (PIN 65) PIN 33 PIN 32 PIN 17 Figure 44. 64-Lead LFCSP Lead Configuration (Bottom View) Rev Page August 2011 ADSP-BF592 PIN 48 PIN 33 PIN 1 PIN 1 INDICATOR PIN 16 ...
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... ADSP-BF592 OUTLINE DIMENSIONS Dimensions in Figure 45 are shown in millimeters. PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 1 For information relating to the CP-64-4 package’s exposed pad, see the table endnotes on 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC TOP VIEW BSC SQ ...
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... ORDERING GUIDE Temperature 1, 2 Model Range ADSP-BF592KCPZ-2 0ºC to +70ºC ADSP-BF592KCPZ 0ºC to +70ºC ADSP-BF592BCPZ –40ºC to +85º RoHS compliant part. 2 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www ...
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... ADSP-BF592 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09574-0-8/11(A) Rev Page August 2011 ...