ADSP-21262SKBCZ-200 Analog Devices, ADSP-21262SKBCZ-200 Datasheet

ADSP-21262SKBCZ-200

Manufacturer Part Number

ADSP-21262SKBCZ-200

Description

LQFP 144/ /200 MHZ 32BIT DSP PROCESSOR

Manufacturer

Analog Devices

Datasheet

1.ADSP-21262SBBCZ-150.pdf (48 pages)

Specifications of ADSP-21262SKBCZ-200

Pack_quantity

189

Comm_code

85423190

Lead_time

Analog

ANAADSP21262SKBC!C

Eccn

3A991A2

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ADSP-21262SKBCZ-200

Manufacturer:

Quantity:

220

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SUMMARY

High performance 32-bit/40-bit floating-point processor

Code compatibility—at assembly level, uses the same

Single-instruction multiple-data (SIMD) computational archi-

High bandwidth I/O—a parallel port, an SPI

DAI incorporates two precision clock generators (PCGs), an

On-chip memory—2M bit of on-chip SRAM and a dedicated

The ADSP-21262 is available in commercial and industrial

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

instruction set as other SHARC DSPs

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

ports, a digital applications interface (DAI), and JTAG

input data port (IDP) that includes a parallel data acquisi-

tion port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

4M bit of on-chip mask-programmable ROM

temperature grades. For complete ordering information,

see

Ordering Guide on Page

PROCESSING

ELEMENT

(PEX)

DAG1

JTAG TEST & EMULATION

46.

PRO CESSING

ELEMENT

DAG2

(PEY)

CORE PROCESSOR

PM ADDRESS BUS

DM ADDRESS BUS

PX REGI STER

TIMER

port, six serial

SEQ UENCER

PROG RAM

INSTRUCTION

Figure 1. Functional Block Diagram

CACHE

48-BIT

DIGITAL APPLICATIONS INTERFACE

RO UTI NG

SIGNAL

UNIT

ACQUISITION PORT

ADDR

SPI PORT (1)

SERIAL PORTS (6)

PARALLEL DATA

PRECISION CLOCK

DATA PORTS (8)

PM DATA BUS

DM DATA BUS

DMA CONTRO LLER

GENERATORS (2)

I/O PROCESSOR

TIMERS (3)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

FAX: 781.461.3113

KEY FEATURES

Serial ports offer left-justified sample-pair and I

At 200 MHz (5 ns) core instruction rate, the ADSP-21262

400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—three independent buses for

Transfers between memory and core at up to four 32-bit

2 2 C HA N N ELS

INPUT

via 12 programmable and simultaneous receive or trans-

mit pins, which support up to 24 transmit or 24 receive I

channels of audio when all six serial ports (SPORTs) are

enabled or six full duplex TDM streams of up to 128

channels per frame

operates at 1200 MFLOPS peak/800 MFLOPS sustained

performance whether operating on fixed- or floating-point

data

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

floating- or fixed-point words per cycle, sustained

2.4G byte/s bandwidth at 200 MHz core instruction rate

and 900M byte/sec is available via DMA

DUAL PORTED MEMORY

DATA

SRAM

1M BIT

BLOCK 0

ROM

2M BIT

(MEMORY MAPPED)

IOD

(32)

DATA BUFFERS

REGISTERS

CO NTROL,

STATUS,

Embedded Processor

IOP

IOA

(18)

DUAL PORTED MEMORY

SRAM

1M BIT

BLO CK 1

GPIO FLAGS/

IRQ /TIMEXP

D A TA BU S / GPIO

CON TR OL/GPIO

ADDR

PARALLEL

AD D R ES S/

PORT

ROM

2M BIT

ADSP-21262

DATA

www.analog.com

SHARC

S support

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