ADUC7019 Analog Devices, ADUC7019 Datasheet

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ADUC7019

Manufacturer Part Number
ADUC7019
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7019

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
14
Adc # Channels
5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7019BCPZ
Quantity:
750
FEATURES
Analog I/O
Microcontroller
Clocking options
Memory
1
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Depending on part model. See Ordering Guide for more information.
Multichannel, 12-bit, 1 MSPS ADC
Fully differential and single-ended modes
0 V to V
12-bit voltage output DACs
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Up to 16 ADC channels
Up to 4 DAC outputs available
REF
analog input range
CMP
XCLKO
ADC11
XCLKI
ADC0
CMP0
CMP1
V
RST
OUT
REF
1
AND PLL
1
OSC
PSM
POR
MUX
12-BIT ADC
BAND GAP
PURPOSE TIMERS
SENSOR
FUNCTIONAL BLOCK DIAGRAM
1MSPS
TEMP
PLA
REF
Precision Analog Microcontroller, 12-Bit
4 GENERAL-
ADuC7019/20/21/22/24/25/26/27/28/29
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
31k × 16 FLASH/EEPROM
2k × 32 SRAM
UART, SPI, I
Figure 1.
ADuC7026
SERIAL I/O
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
On-chip peripherals
Power
Packages and temperature range
Tools
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
2
C
UART, 2× I
Up to 40-pin GPIO port
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator
Programmable logic array (PLA)
External memory interface, up to 512 kB
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP
Fully specified for –40°C to +125°C operation
Low cost QuickStart™ development system
Full third-party support
Analog I/O, ARM7TDMI MCU
JTAG
GPIO
2
C® and SPI serial I/O
12-BIT
12-BIT
12-BIT
12-BIT
DAC
DAC
DAC
DAC
©2005-2011 Analog Devices, Inc. All rights reserved.
EXT. MEMORY
INTERFACE
3-PHASE
PWM
1
DAC0
DAC1
DAC2
DAC3
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
1
H
L
H
L
H
L
1
www.analog.com
1

Related parts for ADUC7019

ADUC7019 Summary of contents

Page 1

... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Precision Analog Microcontroller, 12-Bit ADuC7019/20/21/22/24/25/26/27/28/29 On-chip peripherals UART, 2× 40-pin GPIO port 4× ...

Page 2

... Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Detailed Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 16 ESD Caution................................................................................ 16 Pin Configurations and Function Descriptions ......................... 17 ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17 ADuC7024/ADuC7025 ............................................................. 21 ADuC7026/ADuC7027 ............................................................. 24 ADuC7028................................................................................... 27 ADuC7029................................................................................... 29 Typical Performance Characteristics ........................................... 31 Terminology .................................................................................... 34 ADC Specifications .................................................................... 34 DAC Specifications..................................................................... 34 Overview of the ARM7TDMI Core............................................. 35 Thumb Mode (T) ...

Page 3

... A to Rev. B Added ADuC7028 Part ..................................................... Universal Updated Format.................................................................. Universal Changes to Figure 2...........................................................................5 Changes to Table 1 ............................................................................6 Changes to ADuC7026/ADuC7027 Section ...............................23 ADuC7019/20/21/22/24/25/26/27/28/29 Changes to Figure 21 ......................................................................28 Changes to Figure 32 Caption .......................................................30 Changes to Table 14 ........................................................................35 Changes to ADC Circuit Overview Section................................38 Changes to Programming Section ................................................44 Changes to Flash/EE Control Interface Section..........................45 Changes to Table 24 ...

Page 4

... MicroConverter® family. The parts operate from 2 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7019/20/21/22/24/25/26/27/28/29 are available in a variety of memory models and packages (see Ordering Guide). Rev Page ...

Page 5

... OUT REF BAND GAP REFERENCE P4.6/AD14/PLAO[14] 18 PROG. LOGIC P4.7/AD15/PLAO[15] ARRAY ADuC7019/20/21/22/24/25/26/27/28/ ADuC7026* 12-BIT SAR ADC ADC 1MSPS CONTROL CONTROL TEMP 62kB FLASH/EE (31k × 16 BITS) ARM7TDMI 8192 BYTES USER RAM CMP /IRQ (2k × ...

Page 6

... ADuC7019/20/21/22/24/25/26/27/28/29 SPECIFICATIONS AV = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity 3, 4 Differential Nonlinearity DC Code Distribution ENDPOINT ERRORS 5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE ...

Page 7

... J All digital inputs excluding XCLKI and XCLKO V = IOV except TDI on IL ADuC7019/20/21/22/24/25/ TDI on ADuC7019/20/21/22/24/25/29 IL All logic inputs excluding XCLKI All digital outputs excluding XCLKO I = 1.6 mA SOURCE I = 1.6 mA SINK T = 0°C to 85°C range A ...

Page 8

... Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 14 IOV power supply current decreases typically during a Flash/EE erase cycle the ADuC7019/20/21/22, this current must be added to the AV Min Typ Max Unit 326 kHz 41 ...

Page 9

... HOLD_ADDR_AFTER_AE_L t HOLD_ADDR_BEFORE_WR_L t ADDR_AFTER_CLKH AD[16:1] FFFF 9ABC BLE BHE A16 ADuC7019/20/21/22/24/25/26/27/28/29 Typ UCLK ½ CLK (XMxPAR[14:12 × CLK ½ CLK + (!XMxPAR[10]) × CLK (!XMxPAR[8]) × CLK ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK (XMxPAR[7: × CLK (!XMxPAR[8]) × CLK ½ CLK (!XMxPAR[ × CLK ...

Page 10

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 3. External Memory Read Cycle Parameter Min 1 CLK 1/MD clock t 4 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t RD_L_AFTER_AE_L t 0 RD_H_AFTER_CLKH DATA_BEFORE_RD_H t 8 DATA_AFTER_RD_H t RELEASE_MS_AFTER_RD_H 1 See Table 78. CLK ECLK t MS_AFTER_CLKH MSx t AE_H_AFTER_MS ADDR_AFTER_CLKH AD[16:1] FFFF 2348 BHE BLE ...

Page 11

... Fall time for both CLOCK and SDATA depends on the clock divider or CD bits in the PLLCON MMR. t HCLK t BUF SDATA (I/O) t DSU t PSU SCLK ( STOP START CONDITION CONDITION ADuC7019/20/21/22/24/25/26/27/28/ see Figure 57. HCLK UCLK see Figure 57. HCLK UCLK t SUP MSB ...

Page 12

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 6. SPI Master Mode Timing (Phase Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...

Page 13

... HCLK 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57. UCLK SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) t DOSU MOSI MISO t DSU ADuC7019/20/21/22/24/25/26/27/28/29 Min × t UCLK 2 2 × t UCLK see Figure 57. HCLK UCLK ...

Page 14

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 8. SPI Slave Mode Timing (Phsae Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...

Page 15

... It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57. UCLK 2 t depends on the clock divider or CD bits in the PLLCON MMR. t HCLK SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) t DOCS MISO MOSI t DSU ADuC7019/20/21/22/24/25/26/27/28/29 Min (2 × t HCLK × t UCLK 1 2 × t UCLK see Figure 57. HCLK UCLK ...

Page 16

... ADuC7019/20/21/22/24/25/26/27/28/29 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GND otherwise noted. Table 10. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage to IOGND Digital Output Voltage to IOGND V to AGND REF Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range, Industrial ...

Page 17

... PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADuC7019/ADuC7020/ADuC7021/ADuC7022 BM/P0.0/CMP NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. Figure 10. 40-Lead LFCSP_VQ Pin Configuration (ADuC7019/ADuC7020) BM/P0.0/CMP NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. ADuC7019/20/21/22/24/25/26/27/28/29 ADC3/CMP1 1 PIN 1 ADC4 2 INDICATOR GND 3 REF DAC0/ADC12 4 ADuC7019/ DAC1/ADC13 5 ADuC7020 DAC2/ADC14 6 TOP VIEW ...

Page 18

... DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC3 Voltage Output on ADuC7020. On the ADuC7019 capacitor must be connected between this pin and AGND/Single-Ended or Differential Analog Input 15 (see Figure 43). Test Mode Select, JTAG Test Port Input. Debug and download access. ...

Page 19

... P4.2/PLAO[10] ADuC7019/20/21/22/24/25/26/27/28/29 Description /PLAI[7] Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter OUT serial download mode low at reset and execute code pulled high at reset through a 1 kΩ resistor/General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. ...

Page 20

... V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. Exposed Paddle. The pin configuration for the ADuC7019/ADuC7020/ ADuC7021/ADuC7022 has an exposed paddle that must be left unconnected. Rev Page ...

Page 21

... ADuC7024/ADuC7025 BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. Figure 13. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025) P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] ADuC7019/20/21/22/24/25/26/27/28/29 ADC4 1 PIN 1 ADC5 2 ADC6 3 INDICATOR ADC7 4 ADC8 5 ADuC7024/ ADC9 6 ADuC7025 GND 7 REF ADCNEG 8 TOP VIEW DAC0/ADC12 9 (Not to Scale) DAC1/ADC13 10 TMS ...

Page 22

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 GND REF 8 ADCNEG 9 DAC0/ADC12 10 DAC1/ADC13 11 TMS 12 TDI 13 P4.6/PLAO[14] 14 P4.7/PLAO[15] 15 BM/P0.0/CMP /PLAI[7] OUT 16 P0.6/T1/MRST/PLAO[3] 17 TCK 18 TDO 19 IOGND 20 IOV DGND 23 P3.0/PWM0 /PLAI[8] ...

Page 23

... ADC2/CMP0 64 ADC3/CMP1 0 EP ADuC7019/20/21/22/24/25/26/27/28/29 Description General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/ Programmable Logic Array Input Element 15. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0 ...

Page 24

... ADuC7019/20/21/22/24/25/26/27/28/29 ADuC7026/ADuC7027 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GND REF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2 /BLE H P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMP /PLAI[7]/MS0 OUT Table 13. Pin Function Descriptions (ADuC7026/ADuC7027) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 ADC10 8 GND ...

Page 25

... P0.7/ECLK/XCLK/SPM8/PLAO[4] 44 XCLKO 45 XCLKI ADuC7019/20/21/22/24/25/26/27/28/29 Description JTAG Test Port Input, Test Data In. Debug and download access. General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory Byte Low Enable. General-Purpose Input and Output Port 2.3/External Memory Access Enable. General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic Array Output Element 14 ...

Page 26

... ADuC7019/20/21/22/24/25/26/27/28/29 Pin No. Mnemonic 46 P3.6/AD6/PWM /PLAI[14] TRIP 47 P3.7/AD7/PWM /PLAI[15] SYNC 48 P2.7/PWM1 /MS3 L 49 P2.1/WS/PWM0 /PLAO[ P2.2/RS/PWM0 /PLAO[ P1.7/SPM7/PLAO[0] 52 P1.6/SPM6/PLAI[6] 53 IOGND 54 IOV DD 55 P4.0/AD8/PLAO[8] 56 P4.1/AD9/PLAO[9] 57 P1.5/SPM5/PLAI[5]/IRQ3 58 P1.4/SPM4/PLAI[4]/IRQ2 59 P1.3/SPM3/PLAI[3] 60 P1.2/SPM2/PLAI[2] 61 P1.1/SPM1/PLAI[1] 62 P1.0/T1/SPM0/PLAI[0] 63 P4.2/AD10/PLAO[10] 64 P4.3/AD11/PLAO[11] 65 P4.4/AD12/PLAO[12] 66 P4.5/AD13/PLAO[13] 67 REFGND 68 V REF 69 DAC ...

Page 27

... P4.3/PLAO[11] C6 P4.0/PLAO[8] C7 P4.1/PLAO[9] C8 IOGND D1 ADCNEG D2 GND REF D3 ADC7 D4 P4.4/PLAO[12] D5 P3.6/PWM /PLAI[14] TRIP D6 P1.7/SPM7/PLAO[0] ADuC7019/20/21/22/24/25/26/27/28/ BOTTOM VIEW (Not to Scale) Figure 16. 64-Ball BGA Pin Configuration (ADuC7028) Description Single-Ended or Differential Analog Input 3/Comparator Negative Input. 3.3 V Power Supply for the DACs. Must be connected ...

Page 28

... ADuC7019/20/21/22/24/25/26/27/28/29 Ball No. Mnemonic D7 P1.6/SPM6/PLAI[6] D8 IOV DD E1 DAC3 E2 DAC2 E3 DAC1 E4 P3.0/PWM0 /PLAI[ P3.2/PWM1 /PLAI[10 P1.5/SPM5/PLAI[5]/IRQ3 E7 P3.7/PWM /PLAI[15] SYNC E8 XCLKI F1 P4.6/PLAO[14] F2 TDI F3 DAC0s F4 P3.1/PWM0 /PLAI[ P3.3/PWM1 /PLAI[11 RST F7 P0.7/ECLK/XCLK/SPM8/PLAO[4] F8 XCLKO G1 BM/P0.0/CMP /PLAI[7] OUT G2 P4.7/PLAO[15] G3 TMS G4 TDO G5 P0.3/TRST/ADC BUSY G6 P3 ...

Page 29

... D1 DAC0 D2 DAC3 D3 DAC1 D4 P3.3/PWM1 /PLAI[11 P3.4/PWM2 /PLAI[12 P3.6/PWM /PLAI[14] TRIP D7 P1.7/SPM7/PLAO[0] ADuC7019/20/21/22/24/25/26/27/28/ BOTTOM VIEW (Not to Scale) Figure 17. 49-Ball BGA Pin Configuration (ADuC7029) Description Single-Ended or Differential Analog Input 3/Comparator Negative Input. Single-Ended or Differential Analog Input 1. ...

Page 30

... ADuC7019/20/21/22/24/25/26/27/28/29 Ball No. Mnemonic E1 TMS E2 BM/P0.0/CMP /PLAI[7] OUT E3 DAC2 E4 IOV DD E5 P3.2/PWM1 /PLAI[10 P3.5/PWM2 /PLAI[13 P0.7/ECLK/XCLK/SPM8/PLAO[4] F1 TDI F2 P0.6/T1/MRST/PLAO[3] F3 IOGND F4 P3.1/PWM0 /PLAI[ P3.0/PWM0 /PLAI[ RST F7 P2.0/SPM9/PLAO[5]/CONV START G1 TCK G2 TDO DGND G5 P0.3/TRST/ADC BUSY G6 IRQ0/P0.4/PWM /PLAO[1] TRIP G7 IRQ1/P0 ...

Page 31

... Figure 19. Typical INL Error, f 1.0 0.9 0.8 0.7 WCP 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 20. Typical Worst-Case (Positive (WCP) and Negative (WCN)) INL Error vs 774 kSPS REF S ADuC7019/20/21/22/24/25/26/27/28/29 3000 4000 = 774 kSPS 3000 4000 = 1 MSPS S 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.5 –0.5 –0.6 –0.6 WCN –0.7 –0.7 – ...

Page 32

... ADuC7019/20/21/22/24/25/26/27/28/29 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1161 1162 BIN Figure 24. Code Histogram Plot 774 kSPS –20 –40 –60 –80 –100 –120 –140 –160 0 100 FREQUENCY (kHz) Figure 25. Dynamic Performance –20 –40 –60 –80 –100 –120 – ...

Page 33

... TEMPERATURE (°C) Figure 30. Current Consumption vs. Temperature @ 7.85 7.80 7.75 7.70 7.65 7.60 7.55 7.50 7.45 7.40 – TEMPERATURE (°C) Figure 31. Current Consumption vs. Temperature @ ADuC7019/20/21/22/24/25/26/27/28/29 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 125 –40 Figure 32. Current Consumption vs. Temperature in Sleep Mode 37.4 37.2 37.0 36.8 36.6 36.4 36.2 125 62.25 Figure 33. Current Consumption vs. Sampling Frequency Rev Page 125 TEMPERATURE (°C) 125 ...

Page 34

... ADuC7019/20/21/22/24/25/26/27/28/29 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ ...

Page 35

... Flash/EE, SRAM, and memory mapped registers. EXCEPTIONS ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are ADuC7019/20/21/22/24/25/26/27/28/29 • Normal interrupt or IRQ, which is provided to service general-purpose interrupt handling of internal and external events. ...

Page 36

... ADuC7019/20/21/22/24/25/26/27/28/29 • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: • The longest time the request can take to pass through the synchronizer • The time for the longest instruction to complete (the ...

Page 37

... Access to the AHB is one cycle, and access to the APB is two cycles. All 0x00000004 peripherals on the ADuC7019/20/21/22/24/25/26/27/28/29 are 0x00000000 on the APB except the Flash/EE memory, the GPIOs (see Table 78), and the PWM. Rev Page ...

Page 38

... ADuC7019/20/21/22/24/25/26/27/28/29 0xFFFFFFFF 0xFFFFFC3C PWM 0xFFFFFC00 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 I2C1 0xFFFF0900 0xFFFF0848 I2C0 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND GAP REFERENCE 0xFFFF048C 0xFFFF0448 POWER SUPPLY ...

Page 39

... COMSTA0 1 R 0x0718 COMSTA1 1 R 0x071C COMSCR 1 R/W 0x0720 COMIEN1 1 R/W 0x0724 COMIID1 1 R 0x0728 COMADR 1 R/W 0x072C COMDIV2 2 R/W ADuC7019/20/21/22/24/25/26/27/28/29 Default Value Page Address I2C0 Base Address = 0xFFFF0800 0x00 46 0x0800 0x0804 0x0808 0x080C 0x0600 42 0x0810 0x00 43 0x0814 0x01 43 0x0818 0x00 44 0x081C 0x00000000 44 0x0824 0x00 ...

Page 40

... ADuC7019/20/21/22/24/25/26/27/28/29 Access Address Name Byte Type PLA Base Address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0B04 PLAELM1 2 R/W 0x0B08 PLAELM2 2 R/W 0x0B0C PLAELM3 2 R/W 0x0B10 PLAELM4 2 R/W 0x0B14 PLAELM5 2 R/W 0x0B18 PLAELM6 2 R/W 0x0B1C PLAELM7 2 R/W 0x0B20 PLAELM8 2 R/W 0x0B24 PLAELM9 2 R/W 0x0B28 PLAELM10 2 R/W 0x0B2C PLAELM11 2 R/W 0x0B30 PLAELM12 2 R/W 0x0B34 PLAELM13 2 R/W 0x0B38 PLAELM14 2 R/W 0x0B3C ...

Page 41

... LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 μV when V = 2.5 V REF ADuC7019/20/21/22/24/25/26/27/28/29 The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … − 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 39. 1111 1111 1111 ...

Page 42

... BUSY ADCDAT ADuC7019 The ADuC7019 is identical to the ADuC7020 except for one buffered ADC channel, ADC3, and it has only three DACs. The output buffer of the fourth DAC is internally connected to the ADC3 channel as shown in Figure 43. ADC3 Note that the DAC3 output pin must be connected capacitor to AGND ...

Page 43

... CONV 100 Continuous software conversion. 101 PLA conversion. Other Reserved. ADuC7019/20/21/22/24/25/26/27/28/29 Table 19. ADCCP Register Name Address ADCCP 0xFFFF0504 ADCCP is an ADC positive channel selection register. This MMR is described in Table 20. Table 20. ADCCP ...

Page 44

... This architecture can operate in three modes: differential, pseudo differential, and single-ended. Differential Mode The ADuC7019/20/21/22/24/25/26/27/28/29 each contain a successive approximation ADC based on two capacitive DACs. Figure 44 and Figure 45 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs ...

Page 45

... Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7019/20/21/22/24/25/26/27/28/29. SW2 switches between A (Channel−) and The V REF connected to ground or a low voltage. The input signal on V can then vary from Note that V IN− ...

Page 46

... Voltage) / 1.3) oC\n",b); } BAND GAP REFERENCE Each ADuC7019/20/21/22/24/25/26/27/28/29 provides an on- chip band gap reference of 2.5 V, which can be used for the ADC and DAC. This internal reference also appears on the V When using the internal reference, a 0.47 μF capacitor must be connected from the external V and fast response during ADC conversions ...

Page 47

... The Flash/EE memory can be programmed in-circuit, using the serial download mode or the provided JTAG mode. Serial Downloading (In-Circuit Programming) The ADuC7019/20/21/22/24/25/26/27/28/29 facilitate code download via the standard UART serial port or via the I The parts enter serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 kΩ ...

Page 48

... ADuC7019/20/21/22/24/25/26/27/28/29 SECURITY The Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 42) protects the 62 kB from being read through JTAG programming mode. The other 31 bits of this register protect writing to the flash memory. Each bit protects four pages, that is, 2 kB. Write protection is activated for all types of access ...

Page 49

... Reserved Reserved. 0x0E Reserved Reserved. 0x0F Ping No operation; interrupt generated. 1 The FEECON register always reads 0x07 immediately after execution of any of these commands. ADuC7019/20/21/22/24/25/26/27/28/29 Table 37. FEEDAT Register Access Name Address R/W FEEDAT 0xFFFFF80C FEEDAT is a 16-bit data register. Table 38. FEEADR Register ...

Page 50

... ARM mode with 32-bit wide SRAM instead of 16-bit wide Flash/EE memory. Remap Operation When a reset occurs on the ADuC7019/20/21/22/24/25/26/27/ 28/29, execution automatically starts in the factory-programmed, internal configuration code. This kernel is hidden and cannot be accessed by user code. If the part is in normal mode (the BM ...

Page 51

... If this bit is set, only SRAM is available. 2:1 Reserved. 0 Remap Remap bit. Set by user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000. ADuC7019/20/21/22/24/25/26/27/28/29 Table 46. RSTSTA Register Name Address RSTSTA 0xFFFF0230 Table 47. RSTSTA MMR Bit Designations Bit Description 7:3 Reserved ...

Page 52

... ADuC7019/20/21/22/24/25/26/27/28/29 OTHER ANALOG PERIPHERALS DAC The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two, three, or four 12-bit voltage output DACs on-chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ranges band gap 2.5 V reference DAC ...

Page 53

... Figure 54. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 54 get worse as a function of output loading. Most of the ADuC7019/20/21/22/24/25/26/27/28/29 data sheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 54 become larger ...

Page 54

... OSCILLATOR AND PLL—POWER CONTROL Clocking System ) is one-half the H Each ADuC7019/20/21/22/24/25/26/27/28/29 integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency binary submultiples of it ...

Page 55

... POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; Power Control System A choice of operating modes is available on the ADuC7019/20/ 21/22/24/25/26/27/28/29. Table 57 describes what part is powered on in the different modes and indicates the power-up time. Table 58 gives some typical values of the total current consump- tion (analog + digital supply currents) in the different modes, depending on the clock divider bits ...

Page 56

... ADuC7019/20/21/22/24/25/26/27/28/29 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs: PLLCON (see Table 61) and POWCON (see Table 64). PLLCON controls the operating mode of the clock system, whereas POWCON controls the core clock frequency and the power-down mode. ...

Page 57

... PWM outputs. The size of the pulse on the PWM clock periods. The PWM signals produced by the ADuC7019/20/21/22/24/25/ 26/27/28/29 can be shut off via a dedicated asynchronous PWM shutdown pin, PWM neously places all six PWM outputs in the off state (high). This ...

Page 58

... PWM shutdown via the PWM pin and generates the TRIP correct reset signal for the timing unit. The PWM controller is driven by the ADuC7019/20/21/22/24/ 25/26/27/28/29 core clock frequency and is capable of generating two interrupts to the ARM core. One interrupt is generated on the occurrence of a PWMSYNC pulse, and the other is generated on the occurrence of any PWM shutdown action ...

Page 59

... PWMDAT1 register. PWM Operating Mode (PWMCON and PWMSTA MMRs) As discussed in the 3-Phase PWM section, the PWM controller of the ADuC7019/20/21/22/24/25/26/27/28/29 can operate in two distinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 2 of the PWMCON register. ...

Page 60

... ADuC7019/20/21/22/24/25/26/27/28/29 Both switching edges are moved by an equal amount (PWMDAT1 × preserve the symmetrical output CORE patterns. Also shown are the PWMSYNC pulse and Bit 0 of the PWMSTA register, which indicates whether operation is in the first or second half cycle of the PWM period. ...

Page 61

... PWM outputs by setting Bit 0 and Bit 1 of the PWMEN register. This situation is illustrated in Figure 61, where it can be seen that both the 0H and 1L signals are identical because PWMCH0 = PWMCH1 and the crossover bit for Phase B is set. ADuC7019/20/21/22/24/25/26/27/28/29 PWMCH0 = PWMCH1 0H 2 × PWMDAT1 ...

Page 62

... ADuC7019/20/21/22/24/25/26/27/28/29 The GDCLK value can range from 0 to 255, corresponding to a programmable chopping frequency rate of 40.8 kHz to 10.44 MHz for a 41.78 MHz core frequency. The gate drive features must be programmed before operation of the PWM controller and are typically not changed during normal operation of the PWM controller ...

Page 63

... The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7019/20/21/22/24/25/26/27/28/29 part enters a power-saving mode, the GPIO pins retain their state. Rev Page ...

Page 64

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 78. GPIO Pin Function Descriptions Configuration Port Pin P0.0 GPIO CMP P0.1 GPIO PWM2 H P0.2 GPIO PWM2 L P0.3 GPIO TRST P0.4 GPIO/IRQ0 PWM TRIP P0.5 GPIO/IRQ1 ADC BUSY P0.6 GPIO/T1 MRST P0.7 GPIO ECLK/XCLK 1 P1.0 GPIO/T1 SIN P1.1 GPIO SOUT P1.2 GPIO RTS P1.3 GPIO CTS P1.4 GPIO/IRQ2 RI P1.5 GPIO/IRQ3 DCD P1.6 GPIO DSR P1 ...

Page 65

... CPU. The UART includes a fractional divider for baud rate generation and has a network addressable mode. The UART function is made available on the 10 pins of the ADuC7019/20/ 21/22/24/25/26/27/28/29 (see Table 90). 1 Access W Table 90 ...

Page 66

... ADuC7019/20/21/22/24/25/26/27/28/29 The serial communication adopts an asynchronous protocol, which supports various word lengths, stop bits, and parity generation options selectable in the configuration register. Baud Rate Generation There are two ways of generating the UART baud rate, normal 450 UART baud rate generation and the fractional divider. ...

Page 67

... Word length select five bits six bits seven bits eight bits. Table 102. COMCON1 Register Name Address Default Value COMCON1 0xFFFF0710 0x00 COMCON1 is the modem control register. ADuC7019/20/21/22/24/25/26/27/28/29 Table 103. COMCON1 MMR Bit Descriptions Access Bit Name R 7:5 4 LOOPBACK Clearing Operation ...

Page 68

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 107. COMSTA1 MMR Bit Descriptions Bit Name Description 7 DCD Data carrier detect Ring indicator. 5 DSR Data set ready. 4 CTS Clear to send. 3 DDCD Delta DCD. Set automatically if DCD changed state since last COMSTA1 read. Cleared automati- cally by reading COMSTA1. ...

Page 69

... UART. Upon receiving this address, the device interrupts the processor and/or sets the appropriate status bit in COMIID1. SERIAL PERIPHERAL INTERFACE The ADuC7019/20/21/22/24/25/26/27/28/29 integrate a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex maximum bit rate of 3 ...

Page 70

... ADuC7019/20/21/22/24/25/26/27/28/29 SPI Registers The following MMR registers are used to control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. Table 117. SPISTA Register Name Address Default Value SPISTA 0xFFFF0A00 0x00 SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4 of this register generates an interrupt. Bit 6 of the SPICON register determines which bit generates the interrupt ...

Page 71

... I C-COMPATIBLE INTERFACES The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed interfaces. The I C interfaces are both implemented as a hard- ware master and a full slave interface. Because the two I faces are identical, this data sheet describes only I2C0 in detail. Note that the two masters and one of the slaves have individual interrupts (see the Interrupt System section) ...

Page 72

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 127. I2C0SSTA MMR Bit Descriptions Bit Value Description 31:15 Reserved. These bits should be written Start decode bit. Set by hardware if the device receives a valid start plus matching address. Cleared stop condition general call reset. 13 Repeated start decode bit. Set by hardware if the device receives a valid repeated start and matching address ...

Page 73

... This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7019/20/21/22/24/25/26/27/28/29 watch for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately ...

Page 74

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 138. I2CxDIV Registers Name Address Default Value I2C0DIV 0xFFFF0830 0x1F1F I2C1DIV 0xFFFF0930 0x1F1F I2CxDIV are the clock divider registers. Table 139. I2CxIDx Registers Name Address Default Value I2C0ID0 0xFFFF0838 0x00 I2C0ID1 0xFFFF083C 0x00 I2C0ID2 0xFFFF0840 0x00 I2C0ID3 0xFFFF0844 0x00 ...

Page 75

... Figure 64. PLA Element In total, 30 GPIO pins are available on each ADuC7019/20/21/ 22/24/25/26/27/28/29 for the PLA. These include 16 input pins and 14 output pins, which msut be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. ...

Page 76

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 146. PLACLK Register Name Address Default Value PLACLK 0xFFFF0B40 0x00 PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 44 MHz. ...

Page 77

... PLA Element 15. Table 153. PLADIN Register Name Address Default Value PLADIN 0xFFFF0B4C 0x00000000 PLADIN is a data input MMR for PLA. ADuC7019/20/21/22/24/25/26/27/28/29 Table 154. PLADIN MMR Bit Descriptions Access Bit Description R/W 31:16 Reserved. 15:0 Input bit to Element 15 to Element 0. Table 155. PLADOUT Register ...

Page 78

... ADuC7019/20/21/22/24/25/26/27/28/29 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 23 interrupt sources on the ADuC7019/20/21/22/ 24/25/26/27/28/29 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Four additional interrupt sources are generated from external interrupt request pins, IRQ0, IRQ1, IRQ2, and IRQ3 ...

Page 79

... Note that any interrupt signal must be active for at least the equivalent of the interrupt latency time, which is detected by the interrupt controller and by the user in the IRQSTA/FIQSTA Access register TIMERS The ADuC7019/20/21/22/24/25/26/27/28/29 have four general- purpose timer/counters. Access • R/W Timer0 • Timer1 • ...

Page 80

... ADuC7019/20/21/22/24/25/26/27/28/29 When using an asynchronous clock-to-clock timer, the interrupt in the timer block may take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared before leaving the interrupt service routine. This can be done by checking the IRQSTA MMR ...

Page 81

... Address Default Value T1CLRI 0xFFFF032C 0xFF T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt. ADuC7019/20/21/22/24/25/26/27/28/29 Table 179. T1CAP Register Name Address T1CAP 0xFFFF0330 T1CAP is a 32-bit register. It holds the value contained in T1VAL when a particular event occurs. This event must be selected in T1CON ...

Page 82

... ADuC7019/20/21/22/24/25/26/27/28/29 Table 183. T2CON MMR Bit Descriptions Bit Value Description 31:11 Reserved. 10:9 Clock source. 00 External crystal. 01 External crystal. 10 Internal oscillator Core clock (41 MHz/2 8 Count up. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down by default. 7 Timer2 enable bit. Set by user to enable Timer2. ...

Page 83

... If it fails to match the expected state, a reset is immediately generated, even if the count has not yet expired. ADuC7019/20/21/22/24/25/26/27/28/29 The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read ...

Page 84

... ADuC7019/20/21/22/24/25/26/27/28/29 ADuC7026/ ADuC7027 A16 AD15:AD0 LATCH AE MS0 MS1 WS RS Figure 70. Interfacing to External EEPROM/RAM Table 192. XMCFG Register Name Address Default Value XMCFG 0xFFFFF000 0x00 XMCFG is set enable external memory access. This must be set to 1 before any port pins function as external memory access pins ...

Page 85

... Figure 71. External Memory Read Cycle UCLK AD[16:0] ADDRESS EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) MSx AE RS Figure 72. External Memory Read Cycle with Address Hold and Bus Turn Cycles Rev Page ADuC7019/20/21/22/24/25/26/27/28/29 DATA DATA BUS TURN OUT CYCLE BUS TURN OUT CYCLE (BIT 9) (BIT 9) ...

Page 86

... ADuC7019/20/21/22/24/25/26/27/28/29 UCLK AD[16:0] MSx AE WS Figure 73. External Memory Write Cycle with Address and Write Hold Cycles UCLK AD[16:0] MSx AE WS ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) ADDRESS 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) Figure 74. External Memory Write Cycle with Wait States Rev ...

Page 87

... IOV recommended. 0.1µF and then decoupling DD Linear Voltage Regulator Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single 3.3 V supply, but the core logic requires a 2.6 V supply. An on- 1.6Ω chip linear regulator generates the 2.6 V from IOV 10µF core logic. The LV An external compensation capacitor of 0.47 μF must be connected between LV these pins) to act as a tank of charge as shown in Figure 78 ...

Page 88

... In these cases, tie all the ADuC7019/20/21/ 22/24/25/26/27/28/29 AGND and IOGND pins to the analog ground plane, as illustrated in Figure 79b. In systems with only ...

Page 89

... POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7019/20/21/22/24/25/26/27/28/29. For LV typical, the internal POR holds the part in reset above 2. internal timer times out for, typically, 128 ms before the part is released from reset. The user must ensure that the power supply IOV reaches a stable 2 ...

Page 90

... The serial downloader is a Windows application that allows the user to serially download an assembled program to the on-chip program Flash/EE memory via the serial port on a standard PC. The UART-based serial downloader is included in all the development systems and is usable with the ADuC7019/20/21/ 22/24/25/26/27/28/29 parts that do not contain the I suffix in the Ordering Guide. 2 ...

Page 91

... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ADuC7019/20/21/22/24/25/26/27/28/29 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 84. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad ...

Page 92

... ADuC7019/20/21/22/24/25/26/27/28/29 BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW 9.00 0.60 MAX 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION Figure 86. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...

Page 93

... BALL A1 SQ 4.55 SQ PAD CORNER TOP VIEW DETAIL A * 1.40 MAX 0.15 MIN * COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. Figure 89. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Dimensions shown in millimeters Rev Page ADuC7019/20/21/22/24/25/26/27/28/29 14.20 14.00 SQ 13.80 1.60 MAX PIN 1 12.20 12.00 SQ TOP VIEW 11 ...

Page 94

... ADuC7019/20/21/22/24/25/26/27/28/29 1.20 MAX 5.05 5. BALL A1 INDICATOR 3.90 TOP VIEW BSC SQ BOTTOM 0.65 VIEW DETAIL A BSC DETAIL A 0.35 0.20 0.45 0.40 0.35 BALL DIAMETER Figure. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-49-1) Dimensions shown in millimeters Rev Page CORNER INDEX AREA 0.55 BSC 1 ...

Page 95

... ADuC7027BSTZ62-RL 16 ADuC7027BSTZ62I 16 ADuC7027BSTZ62I-RL 16 ADuC7028BBCZ62 8 4 ADuC7028BBCZ62- ADuC7029BBCZ62 7 4 ADuC7029BBCZ62- ADuC7029BBCZ62I 7 4 ADuC7029BBCZ62I- ADuC7019/20/21/22/24/25/26/27/28/29 FLASH/ Down- Temperature RAM GPIO loader Range −40°C to +125° kB −40°C to +125° kB −40°C to +125°C ...

Page 96

... Z = RoHS Compliant Part. 2 Models ADuC7026 and ADuC7027 include an external memory interface. 3 One of the ADC channels is internally buffered for ADuC7019 models refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). ©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

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