ADUC7121 Analog Devices, ADUC7121 Datasheet
ADUC7121
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ADUC7121 Summary of contents
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... SAR ADC BUF V _2.5 REF P0.0 TO P0.7 P1.0 TO P1.7 Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Analog I/O, ARM7TDMI MCU ADuC7121 2 C and SPI serial I/O IDAC0 IDAC1 IDAC2 IDAC3 IDAC4 PLA OSC PLL POR PWM 8kB SRAM 3× GP (2k × 32-BIT) ...
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... ADuC7121 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Terminology .................................................................................... 20 ADC Specifications .................................................................... 20 DAC Specifications..................................................................... 20 Overview of the ARM7TDMI Core............................................. 21 Thumb Mode (T)........................................................................ 21 Long Multiply (M)...................................................................... 21 EmbeddedICE (I) ....................................................................... 21 Exceptions ...
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... REVISION HISTORY 1/11—Revision 0: Initial Version Rev Page ADuC7121 ...
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... The device operates from 3 3.6 V, and it is specified over an industrial temperature range of −10°C to +95°C. The IDACs are powered from a separate 2 V input power supply. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7121 is available in a 108-ball chip scale package ball grid array [CSP_BGA]. Rev Page ...
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... Buffer enabled μA pF During ADC acquisition buffer bypassed pF During ADC acquisition buffer enabled 28.3 kΩ resistor, PGA gain = 3, acquisition time = 3.2 μs, pseudo differential mode μA nA Bits 0.1% accuracy, 5 ppm external resistor for current to voltage % ppm/°C nA PGA offset not included pA/°C V ADuC7121 /2 ADC = 1 MSPS, ...
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... ADuC7121 Parameter PADC1 INPUT Full-Scale Input Range 4 Input Leakage at PADC1x Resolution 4 Gain Error 4 Gain Drift 4 Offset 4 Offset Drift PADC1x-Compliant Range ON-CHIP VOLTAGE REFERENCE Output Voltage 7 Accuracy 4 Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal V Power-On Time REF EXTERNAL REFERENCE INPUT ...
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... Bits LSB LSB Guaranteed monotonic mV 2.5 V internal reference mV Measured at Code full scale on DAC0 μs Buffered μV/°C μV/°C mA Buffer on V/μs μs nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) ADuC7121 ...
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... ADuC7121 Parameter 11 TEMPERATURE SENSOR Voltage Output at 25°C Voltage Temperature Coefficient Accuracy POWER SUPPLY MONITOR (PSM) IOV Trip Point Selection DD Power Supply Trip Point Accuracy POWER-ON RESET WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance 12 13 Data Retention DIGITAL INPUTS Logic 1 Input Current ...
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... JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. J Rev Page Unit Test Conditions/Comments Code executing from Flash/ (41.78 MHz clock (41.78 MHz clock) μ 25° MSPS mA All current DACs (IDACs) on μA per VDAC 2.5 V reference 25° ADuC7121 ...
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... ADuC7121 TIMING SPECIFICATIONS 2 Table Timing in Fast Mode (400 kHz) Parameter Description t SCL low pulse width L t SCL high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time DHD t Setup time for repeated start RSU ...
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... DAV MSB BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 t DSU t DHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev Page ADuC7121 Typ Max (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 25 UCLK UCLK 5 12.5 5 12.5 5 12 ...
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... ADuC7121 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SPICLK low pulse width SL t SPICLK high pulse width SH t Data output valid after SPICLK edge DAV t Data output setup before SPICLK edge DOSU t Data input setup time before SPICLK edge ...
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... DAV MSB BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 t DSU t DHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev Page ADuC7121 Typ Max (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 25 UCLK UCLK 5 12.5 5 12.5 5 12.5 5 12.5 t SFS t ...
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... ADuC7121 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SPICLK edge CS t SPICLK low pulse width SL t SPICLK high pulse width SH t Data output valid after SPICLK edge DAV t Data input setup time before SPICLK edge DSU t Data input hold time after SPICLK edge ...
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... Only one absolute maximum rating can be applied at any one time. −0 IOV + 0 −0 0 −0 0.3 V ESD CAUTION DD −0 0 −10°C to +95°C −65°C to +150°C 150°C 40°C/W 240°C 260°C Rev Page ADuC7121 ...
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... D3 P0.3/MISO/PLAO[12]/SYNC E3 P0.4/MOSI/PLAI[11]/TRIP F3 P0.5/CS/PLAI[10]/ADC CONVST G3 P0.6/MRST/PLAI[2] G10 P0.7/TRST/PLAI[ ADuC7121 F G TOP VIEW Figure 7. Pin Configuration 1 Type Description I Reset Input (Active Low). I/O General-Purpose Input and Output Port 0.0 (P0.0). ...
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... External Interrupt Request 3, Active High (IRQ3). Programmable Logic Array for Input Element 15 (PLAI[15]). I/O General-Purpose Input and Output Port 2.7 (P2.7). I/O General-Purpose Input and Output Port 3.0 (P3.0). Programmable Logic Array for Output Element 0 (PLAO[0]). I/O General-Purpose Input and Output Port 3.1 (P3.1). Programmable Logic Array for Output Element 1 (PLAO[1]). Rev Page ADuC7121 ...
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... ADuC7121 Pin No. Mnemonic D1 P3.2/IRQ4/PWM3/PLAO[2] E1 P3.3/IRQ5/PWM4/PLAO[3] E2 P3.4/PLAO[8] F2 P3.5/PLAO[9] D12 P3.6/PLAO[10] E12 P3.7/BM/PLAO[11 _2.5 REF L5 V _1.2 REF B8 I REF K6 BUF_VREF1 K7 BUF_VREF2 L6 PADC0P M5 PADC0N L7 PADC1P M8 PADC1N ADC4 M3 ADC5 M10 ADC6 M9 ADC7 L9 ADC8 K9 ADC9 K8 ADC10/AINCM K1 DAC0 K2 DAC1 ...
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... Crystal Oscillator Inverter Input and Internal Clock Generator Circuits Input external crystal is not being used, connect this pin to the DGND system ground. DI JTAG Test Port Input, Test Clock. Debug and download access. DI JTAG Test Port Input, Test Mode Select. Debug and download access. Rev Page ADuC7121 ...
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... ADuC7121 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity Integral nonlinearity (INL) is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ ...
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... Attempted execution of an undefined instruction. • Software interrupt instruction (SWI). This can be used to make a call to an operating system. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. Rev Page ADuC7121 ...
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... ADuC7121 ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and 6 status registers. Each operating mode has dedicated banked registers. When writing user level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15), and the cur- rent program status register (CPSR) are usable. The remaining registers are used for system level programming and exception handling only ...
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... Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7121 are on the APB except the Flash/EE memory and the GPIOs. Rev Page ADuC7121 ...
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... ADuC7121 0xFFFF0746 IDAC 0xFFFF0700 0xFFFF05DF DAC 0xFFFF0580 0xFFFF0524 ADC 0xFFFF0500 0xFFFFFFFF 0xFFFF04A8 0xFFFF0FBC BANDGAP REFERENCE 0xFFFF0480 0xFFFF0F80 0xFFFF0448 0xFFFF0EA8 POWER SUPPLY MONITOR 0xFFFF0440 0xFFFF0E80 0xFFFF0418 0xFFFF0E28 PLL AND OSCILLATOR CONTROL 0xFFFF0400 0xFFFF0E00 0xFFFF0394 0xFFFF0D78 GENERAL PURPOSE TIMER 4 0xFFFF0D00 0xFFFF0380 0xFFFF0370 0xFFFF0B54 ...
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... R/W 2 0x08CC R/W 2 Table 21. I R/W 2 Address R/W 2 0x0900 R/W 2 0x0904 R/W 2 0x0908 R/W 2 0x090C R/W 2 0x0910 R/W 2 0x0914 R/W 2 0x0918 R/W 2 0x091C R/W 2 0x0920 R/W 2 Rev Page ADuC7121 Name Byte Access Type IDAC4DAT 4 R/W IDAC4BW 1 R/W TSDCON 1 R/W IDACSTA 1 R/W IDAC0PULLDOWN 1 R/W Name Byte Access Type COMTX 1 W COMRX 1 R COMDIV0 1 R/W COMIEN0 1 R/W COMDIV1 1 R/W COMIID0 1 R COMCON0 ...
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... ADuC7121 Address Name Byte Access Type 0x0924 I2C1DIV 2 R/W 0x0928 I2C1SCTL 2 R/W 0x092C I2C1SSTA 2 R 0x0930 I2C1SRX 1 R 0x0934 I2C1STX 1 W 0x0938 I2C1ALT 1 R/W 0x093C I2C1ID0 1 R/W 0x0940 I2C1ID1 1 R/W 0x0944 I2C1ID2 1 R/W 0x0948 I2C1ID3 1 R/W 0x094C I2C1FSTA 1 R/W Table 22. SPI Base Address = 0xFFFF0A00 Address Name Byte 0x0A00 SPISTA ...
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... ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C. The ADuC7121 is modified in a way that differentiates its ADC structure from other devices in the ADuC702x family. The PADC0x and PADC1x inputs connect to a PGA and allow for a gain from with 32 steps ...
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... AV DD input buffer must be bypassed. The ADuC7121 provides two pins for each thermistor input. The negative input removes the error of the ground difference. When selecting the thermistor input, always bypass the negative side buffer to ensure that the amplifier is not saturated. Configure the ADC to work in positive pseudo differential mode ...
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... ADCDAT ADCSTA = 0 Figure 16. ADC Timing TEMPERATURE SENSOR The ADuC7121 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature ...
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... ADuC7121 Table 29. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00) Bit Value Description 31:16 These bits are reserved. 15 Positive ADC buffer bypass. 0 Set the user to enable the positive ADC buffer. 1 Set the user to bypass the positive ADC buffer. 14 Negative ADC buffer bypass. ...
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... Differential Mode The ADuC7121 contains a successive approximation ADC based on two capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs ...
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... AIN11 B V REF Figure 19. ADC Conversion Phase Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V input of the ADuC7121, and SW2 switches between A (Channel−) and The V input must be connected to REF IN− ground or a low voltage. The input signal on V ...
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... Set by the user to connect the internal 1.2 V reference to the V Cleared by the user to disconnect the reference from the V BAND GAP REFERENCE The ADuC7121 provides an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This 2.5 V refer- ence is generated from a 1.2 V reference. ...
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... ADuC7121 POWER SUPPLY MONITOR The power supply monitor on the ADuC7121 indicates when the IOVDD supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR. ...
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... Figure 25. Flash/EE Memory Data Retention Serial Downloading (In-Circuit Programming) The ADuC7121 facilitates code download via the I port. The ADuC7121 enters serial download mode after a reset or power cycle if the BM function of the P3.7/ BM /PLAO[11] pin is pulled low through an external 1 kΩ resistor. This is combined with the state of Address 0x00014 in the flash. If this address is 0xFFFFFFFF and BM is pulled low, the part enters download mode ...
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... ADuC7121 writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID similarly protect the second 64 kB block. All 32 bits of this are used to protect four pages at a time. Three Levels of Protection Protection can be set and removed by writing directly into the FEExHID MMR ...
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... Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading FEExSTA register. 2 Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Rev Page ADuC7121 ...
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... ADuC7121 Bit Description 1 Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading FEExSTA register. 0 Command complete. Set by MicroConverter when a command is complete. Cleared automatically when reading FEExSTA register. FEE0MOD Register Name: FEE0MOD Address: 0xFFFF0E04 Default value: 0x80 Access: Read and write ...
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... When a reset occurs on the ADuC7121, execution starts auto- matically in factory programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADuC7121 is in normal mode (the P3.7/ BM /PLAO[11] pin is high), it executes the power-on configuration routine of the kernel and then jumps to the Reset Vector Address 0x00000000 to execute the user’ ...
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... ADuC7121 Reset Operation There are four types of reset: external reset, power-on reset, watchdog expiration, and software force. The RSTSTA register indicates the source of the last reset and RSTCLR clears the RSTSTA register. These registers can be used during a reset Table 47. Remap MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00) ...
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... OTHER ANALOG PERIPHERALS DIGITAL-TO-ANALOG CONVERTERS The ADuC7121 incorporates four buffered 12-bit voltage output string digital-to-analog converters (DACs) on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ranges band gap 2.5 V reference ...
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... ADuC7121 Table 49 DACxCON Registers (Default Value = 0x100, Read/Write Access) Name DAC0CON DAC1CON DAC2CON DAC3CON Table 50. DAC0CON MMR Bit Designations Bit Value Name Description 15:9 0 Reserved DACPD DAC power-down. Set by the user to set DACOUTx to tristate mode DACBUF_LP DAC buffer low power mode. Set by the user to place DAC_BUFF into a low power mode. ...
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... LDO. The DVDD pin has no reverse battery, current limit, or thermal shutdown protection; therefore essential that users of the ADuC7121 do not short this pin to ground at any time during normal operation or during board manufacture. CURRENT OUTPUT DACs (IDAC) ), the lower nonlinearity ...
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... ADuC7121 The reference current of each IDAC is generated by a precision internal band gap voltage reference and an external precision resistor, and as such, the gain error of each IDAC is impacted by the accuracy of the external resistor. Connect the resistor to the I pin. The noise of each IDAC is limited by its damping ...
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... Reserved Table 55. TDSCON MMR Bit Designations Bit Value 7 Rev Page ADuC7121 PVDD BUF I OUT PGND Value Description 1 IDAC power-down bit. Set by the user power down the IDAC. IDAC output is high impedance. Set by the user power up the IDAC ...
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... EXTRESLOW OSCILLATOR AND PLL—POWER CONTROL The ADuC7121 integrates a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency binary submultiples of it, to allow for power saving ...
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... POWKEY2 = 0xF4; Power Control System A choice of operating modes is available on the ADuC7121. Table 63 describes what part of the ADuC7121 is powered on in the different modes and indicates the power-up time. Table 64 gives some typical values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits ...
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... ADuC7121 Table 63. Operating Modes Mode Core Peripherals Active On On Pause On Nap Sleep Stop Table 64. Typical Current Consumption at 25°C PC[2:0] Mode 000 Active 33.1 001 Pause 22.7 010 Nap 3.8 011 Sleep 0.4 100 Stop 0.4 PLL XTAL/Timer2/Timer3 21.2 13.8 10 13.3 8.5 6.1 3.8 3.8 3.8 0.4 0.4 0.4 0.4 0.4 0.4 Rev Page ...
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... Rev Page ADuC7121 Description Reserved. Operating modes. Active mode. Pause mode. Nap mode. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7121. Stop mode. Reserved. Reserved. CPU clock divider bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. ...
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... ADuC7121 DIGITAL PERIPHERALS PWM GENERAL OVERVIEW The ADuC7121 integrates a 6-channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins ...
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... Enables H-bridge mode. Set the user to enable H-Bridge mode and Bits[5:2] of PWMCON1. Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. Rev Page ADuC7121 ...
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... ADuC7121 In H-bridge mode, HMODE = 1 and Table 69 determine the PWM outputs, as listed in Table 70. Table 70. PWM Output Selection PWMCOM1 MMR PWM Outputs ENA HOFF POINV DIR PWM1 PWM2 ...
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... The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7121 device enters a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 73 ...
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... ADuC7121 Table 73. GPIO Pin Function Designations Port Pin 00 0 P0.0 GPIO P0.1 GPIO P0.2 GPIO P0.3 GPIO P0.4 GPIO P0.5 GPIO P0.6 GPIO P0.7 GPIO 1 P1.0 GPIO P1.1 GPIO 1 P1.2 TDI (JTAG) 1 P1.3 TDO (JTAG) P1.4 GPIO P1.5 GPIO P1.6 GPIO P1.7 GPIO 2 P2.0 GPIO/IRQ0 P2.1 GPIO/IRQ1 P2.2 GPIO P2.3 GPIO/IRQ2 P2.4 GPIO P2.5 GPIO P2.6 GPIO/IRQ3 P2.7 GPIO 3 P3.0 GPIO P3.1 GPIO P3.2 GPIO/IRQ4 P3.3 GPIO/IRQ5 P3.4 GPIO P3.5 GPIO P3 ...
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... Name: GP0DAT Address: 0xFFFF0D20 Default value: 0x000000XX Access: Read and write Name: GP1DAT Address: 0xFFFF0D30 Default value: 0x000000XX Access: Read and write Name: GP2DAT Address: 0xFFFF0D40 Default value: 0x000000XX Access: Read and write Rev Page ADuC7121 ...
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... ADuC7121 Name: GP3DAT Address: 0xFFFF0D50 Default value: 0x000000XX Access: Read and write Table 76. GPxDAT MMR Bit Designations Bit Description 31:24 Direction of the data. Set the user to configure the GPIO pin as an output. Cleared the user to configure the GPIO pin as an input. ...
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... GPIO Px.1 open collector enable. Set the user to enable open collector. Set the user to disable the open collector. 0 GPIO Px.0 open collector enable. Set the user to enable open collector. Set the user to disable the open collector. Rev Page ADuC7121 ...
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... BAUD RATE GENERATION The ADuC7121 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC7121 fractional divider. Normal 450 UART Baud Rate Generation The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL) ...
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... Name: COMDIV1 Address: 0xFFFF0804 Default value: 0x00 Access: Read and write UART Control Register 0 This 8-bit register controls the operation of the UART in conjunction with COMCON1. Name: COMCON0 Address: 0xFFFF080C Default value: 0x00 Access: Read and write Rev Page ADuC7121 ...
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... ADuC7121 Table 81. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 STOP WLS UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: COMCON1 Address: 0xFFFF0810 Default value: 0x00 Access: Read and write Description Divisor latch access ...
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... Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data are overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. Rev Page ADuC7121 ...
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... UART Fractional Divider Register This 16-bit register controls the operation of the fractional divider for the ADuC7121. Name: COMDIV2 Address: 0xFFFF082C Default value: 0x0000 Access: Read and write Table 86. COMDIV2 MMR Bit Designations Bit Name Description 15 FBEN Fractional baud rate generator enable bit ...
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... FIFOs. Status bits are available to the user to control these FIFOs. 2 Configuring External Pins for I C Functionality 2 The I C pins of the ADuC7121 device are P0.0 and P0.1 for C0, and P1.0 and P1.1 for I C1. P0.0 and P1.0 are the I 2 signals, and P0.1 and P1.1 are the I C data signals ...
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... ADuC7121 • I2CxADR0[0] is the read/ write bit REGISTERS 2 The I C peripheral interfaces consists of a number of MMRs. These are described in the following section Master Registers Master Control Register 2 This 16-bit MMR configures I C peripheral in master mode. Name: I2C0MCTL, I2C1MCTL ...
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... I2CMTFSTA I C master Tx FIFO status bits master Tx FIFO empty one byte in master Tx FIFO one byte in master Tx FIFO master Tx FIFO full bus master is unsuccessful in gaining control of the I Rev Page ADuC7121 2 C bus. If the I2CALENI bit in ...
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... ADuC7121 Master Receive Registers 2 This 8-bit MMR is the I C master receive register. Name: I2C0MRX, I2C1MRX Address: 0xFFFF0888, 0xFFFF0908 Default value: 0x00 Access: Read only Master Transmit Registers 2 This 8-bit MMR is the I C master transmit register. Name: I2C0MTX, I2C1MTX Address: ...
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... These bits control the duration of the low period of SCL Slave Registers Slave Control Register 2 C clock generated by This 16-bit MMR configures the I Name: Address: Default value: Access: Rev Page ADuC7121 2 C peripheral in slave mode. I2C0SCTL, I2C1SCTL 0xFFFF08A8, 0xFFFF0928 0x0000 Read and write ...
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... This is a “to whom it may concern” call. The ADuC7121 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written per the I Set this bit and I2CGCEN to enable hardware general call recognition in slave mode ...
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... This bit sets to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the following conditions acknowledge was returned because there was no data in the Tx FIFO. If the I2CNACKEN bit was set in the I2CxSCTL register. This bit is cleared in all other conditions. Rev Page ADuC7121 ...
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... ADuC7121 Bit Name Description 4 I2CSRxFO Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions I2CSRXQ I C slave receive request bit. This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CxSCTL is set ...
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... Read and write Name: I2C1ID1 Address: 0xFFFF0940 Default value: 0x00 Access: Read and write Name: I2C1ID2 Address: 0xFFFF0944 Default value: 0x00 2 C bus Access: Read and write Name: I2C1ID3 Address: 0xFFFF0948 Default value: 0x00 Access: Read and write Rev Page ADuC7121 ...
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... ADuC7121 COMMON REGISTERS FIFO Status Registers These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes. Name: I2C0FSTA Address: 0xFFFF08CC Default value: 0x0000 Access: Read and write Name: I2C1FSTA Address: 0xFFFF094C Default value: 0x0000 Access: Read and write Table 96 ...
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... CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY The SPI pins of the ADuC7121 device are P0.2 to P0.5. • P0.5/ CS /PLAI[10]/ADC slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer ...
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... ADuC7121 Table 97. SPISTA MMR Bit Designations Bit Name Description 15:12 Reserved bits. 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE. ...
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... Set by the user to enable master mode. Cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI. pin is asserted and remains asserted for the duration of each 8-bit serial CONVST Rev Page ADuC7121 ...
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... This is represented in Figure 36 LOOKUP TABLE Figure 36. PLA Element In total, 32 GPIO pins are available on each ADuC7121 for the PLA. These include 16 input pins and 16 output pins, which need Table 99. Element Input/Output PLA Block 0 Element Input 0 P2 ...
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... Element 9 Element 3 Element 11 Element 5 Element 13 Element 7 Element 15 Rev Page ADuC7121 Description Reserved. Mux 0 control (see Table 104). Mux 1 control (see Table 104). Mux 2 control. Set by the user to select the output of Mux 0. Cleared by the user to select the bit value from PLADIN. ...
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... ADuC7121 PLACLK Register PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. The maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Name: PLACLK Address: 0xFFFF0B40 Default value: 0x00 Access: Read and write Table 103. PLACLK MMR Bit Descriptions ...
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... PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Name: PLALCK Address: 0xFFFF0B54 Default value: 0x00 Access: Write only Rev Page ADuC7121 ...
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... PLA IRQ0 27 PLA IRQ1 There are 27 interrupt sources on the ADuC7121 that are con- trolled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types only: a normal interrupt request (IRQ) and a fast interrupt request (FIQ) ...
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... FIQ exception. When a bit is set to 0, the corre- sponding source request is disabled or masked, which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. FIQEN Register Name: FIQEN Address: 0xFFFF0108 Default value: 0x00000000 Access: Read and write Rev Page ADuC7121 ...
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... UNUSED Figure 37. Interrupt Structure Vectored Interrupt Controller (VIC) The ADuC7121 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. ...
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... Flash1PI 11 Reserved 10:8 Flash0PI 7:3 Reserved 2:0 PSMPI Rev Page ADuC7121 Description Reserved bit. A priority level can be set for an IDAC fault interrupt. Reserved bit. A priority level can be set for Timer4. Reserved bit. A priority level can be set for Timer3 ...
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... ADuC7121 IRQP2 Register Name: IRQP2 Address: 0xFFFF0028 Default value: 0x00000000 Access: Read and write Table 114. IRQP2 MMR Bit Designations Bit Name Description 31 Reserved Reserved bit. 30:28 PWMPI A priority level can be set for PWM. 27 Reserved Reserved bit. 26:24 IRQ3PI A priority level can be set for IRQ3. ...
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... Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. EXTERNAL INTERRUPTS (IRQ0 TO IRQ3) The ADuC7121 provides up to six external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, first, the appropriate bit must be set in the FIQEN or IRQEN register ...
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... ADuC7121 Bit Value Name 5:4 11 IRQ2SRC[1: 3:2 11 IRQ1SRC[1: 1:0 11 IRQ0SRC[1: IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default value: 0x00000000 Access: Read and write Description External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. ...
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... TIMERS The ADuC7121 has five general purpose timers/counters. • Timer0 • Timer1 • Timer2 or wake-up timer • Timer3 or watchdog timer • Timer4 The five timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decrements/increments from the maximum/minimum value until zero scale/full scale and starts again at the maximum/minimum value ...
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... ADuC7121 Timer0 Capture Register This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; available in 16-bit mode only. Name: T0CAP Address: 0xFFFF0314 Default value: 0x0000 Access: Read only Timer0 Control Register This 17-bit MMR configures the mode of operation of Timer0. ...
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... Cleared by the user to operate in free-running mode (default). 5:4 Format. 00 Binary (default). 01 Reserved. 10 Hr:Min:Sec:Hundredths: 23 hours to 0 hour. 11 Hr:Min:Sec:Hundredths: 255 hours to 0 hour. 3:0 Prescaler. 0000 Source clock divide-by-1 (default). 0100 Source clock divide-by-16. 1000 Source clock divide-by-256. 1111 Source clock divide-by-32,768. Rev Page ADuC7121 ...
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... ADuC7121 TIMER2—WAKE-UP TIMER Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768 ...
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... Default value: Access: Timer3 Control Register The 16-bit MMR configures the mode of operation of Timer3 and is described in detail in Table 129. Name: Address: Default value: Access: Rev Page ADuC7121 T3LD 0xFFFF0360 0x3BF8 Read and write T3VAL 0xFFFF0364 0x3BF8 Read only T3CLRI 0xFFFF036C ...
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... ADuC7121 Table 129. T3CON MMR Bit Designations Bit Value Description 16:9 These bits are reserved and should be written user code. 8 Count up/down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. 7 Timer3 enable. Set by user code to enable Timer3. ...
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... This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Name: T4CAP Address: 0xFFFF0390 Default value: 0x00000000 Access: Read only Timer4 Control Register This 32-bit MMR configures the mode of operation of Timer4. Name: T4CON Address: 0xFFFF0388 Default value: 0x0000 Access: Read and write Rev Page ADuC7121 ...
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... ADuC7121 Table 130. T4CON MMR Bit Designations Bit Value Description 31:18 Reserved. Set by the user Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. 16:12 Event select range 31. The events are described in the introduction to the Timers section. ...
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... EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 40. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-108-4) Dimensions shown in millimeters Package Description 108-Ball CSP_BGA 108-Ball CSP_BGA, 13” Tape and Reel ADuC7121 QuickStart Development System Rev Page BALL CORNER ...
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... ADuC7121 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09492-0-1/11(0) Rev Page ...