ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 69

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

I
These 16-bit MMRs are the I
Name:
Address:
Default value:
Access:
Table 95. I2CxSSTA MMR Bit Designations
Bit
15
14
13
12:11
10
9:8
7
6
5
2
C Slave Status Registers
Name
I2CSTA
I2CREPS
I2CID[1:0]
I2CSS
I2CGCID[1:0]
I2CGC
I2CSBUSY
I2CSNA
I2C0SSTA, I2C1SSTA
0xFFFF08AC, 0xFFFF092C
0x0000, 0x0000
Read and write
Description
Reserved bit.
This bit is set to 1 if:
A start condition followed by a matching address is detected.
A start byte (0x01) is received.
General calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
I
[00] = Received address matches I2CxID0.
[01] = Received address matches I2CxID1.
[10] = Received address matches I2CxID2.
[11] = Received address matches I2CxID3.
I
This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI
bit in I2CxSCTL is set, an interrupt is generated.
This bit is cleared by reading this register.
I
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL. Note that these bits are not cleared by a general call
reset command.
I
This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset
command, all registers return to their default state. If the command received was a hardware general call, the Rx
FIFO holds the second byte of the command and this can be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
I
Set to 1 when the slave receives a start condition.
Cleared by hardware under the following conditions:
The received address does not match any of the I2CxIDx registers.
The slave device receives a stop condition.
A repeated start address does not match any of the I2CxIDx registers.
I
This bit sets to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the
following conditions:
If no acknowledge was returned because there was no data in the Tx FIFO.
If the I2CNACKEN bit was set in the I2CxSCTL register.
This bit is cleared in all other conditions.
2
2
2
2
2
2
C address matching register. These bits indicate which I2CxIDx register matches the received address.
C stop condition after start detected bit.
C general call ID bits.
C general call status bit.
C slave busy status bit.
C slave no acknowledge data bit.
2
C status registers in slave mode.
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ADuC7121