ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 38

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
Bit
1
0
FEE0MOD Register
Name:
Address:
Default value:
Access:
FEE1MOD Register
Name:
Address:
Default value:
Access:
Table 45. Command Codes in FEExCON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
The FEExCON register always reads 0x07 immediately after execution of any of these commands.
1
1
1
1
1
1
1
Description
Command fail.
Set automatically when a command completes
unsuccessfully.
Cleared automatically when reading FEExSTA register.
Command complete.
Set by MicroConverter when a command is complete.
Cleared automatically when reading FEExSTA register.
Command
Null
Single read
Single write
Erase/write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Reserved
Reserved
Ping
FEE0MOD
0xFFFF0E04
0x80
Read and write
FEE1MOD
0xFFFF0E84
0x80
Read and write
Description
Idle state.
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20
ms.
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA Bit 1.
Erase the page indexed by FEExADR.
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
Reserved.
Reserved.
Reserved.
Reserved.
Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06)
or with the key.
Reserved.
Reserved.
No operation, interrupt generated.
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Table 44. FEExMOD MMR Bit Designations
Bit
7:5
4
3
2
1:0
FEE0CON Register
Name:
Address:
Default value:
Access:
FEE1CON Register
Name:
Address:
Default value:
Access:
Description
Reserved. These bits are always set to 0 except when
writing keys. See the Sequence to Write the Key to
Protection Registers section for details.
Flash/EE interrupt enable.
Set by the user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by the user to disable the Flash/EE interrupt.
Erase/write command protection.
Set by the user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against
erase/write command.
Reserved. The user must set this bit to 0.
Flash/EE wait states. Both Flash/EE blocks must have the
same wait state value for any change to take effect.
FEE0CON
0xFFFF0E08
0x00
Read and write
FEE1CON
0xFFFF0E88
0x00
Read and write