ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 84

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 114. IRQP2 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7
6:4
3
2:0
IRQP3 Register
Name:
Address:
Default value:
Access:
IRQP3 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
Name
Reserved
PWMPI
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
I2C1SPI
Reserved
I2C1MPI
Reserved
I2C0SPI
Name
Reserved
PLA1PI
Reserved
PLA0PI
Reserved
IRQ5PI
Reserved
IRQ4PI
IRQP2
0xFFFF0028
0x00000000
Read and write
IRQP3
0xFFFF002C
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for PWM.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for I
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I
master.
Reserved bit.
A priority level of 0 to 7 can be set for I
slave.
Description
Reserved bit.
A priority level of 0 to 7 can be set for PLA0.
Reserved bit.
A priority level of 0 to 7 can be set for PLA0.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ5.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ4.
2
2
2
C1
C1
C0
Rev. 0 | Page 84 of 96
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and prioritiza-
tion of IRQ interrupts the other to enable nesting and prioritization
of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs can still be used,
but it is not possible to nest IRQs or FIQs, nor is it possible to
set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
Address:
Default value:
Access:
Table 115. IRQCONN MMR Bit Designations
Bit
31:2
1
0
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depends on the
priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts,
Priority 1 then Bit 1 asserts, and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
Address:
Default value:
Access:
Table 116. IRQSTAN MMR Bit Designations
Bit
31:8
7:0
Name
Reserved
ENFIQN
ENIRQN
Name
Reserved
IRQCONN
0xFFFF0030
0x00000000
Read and write
IRQSTAN
0xFFFF003C
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts.
Clearing this bit means no nesting or
prioritization of FIQs is allowed.