ADUC7124 Analog Devices, ADUC7124 Datasheet

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ADUC7124

Manufacturer Part Number
ADUC7124
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7124

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
32000Bytes
Gpio Pins
30
Adc # Channels
12
FEATURES
Analog input/output
Microcontroller
Clocking options
Memory
Vectored interrupt controller for FIQ and IRQ
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Multichannel, 12-bit, 1 MSPS ADC
Fully differential and single-ended modes
0 V to V
12-bit voltage output DACs
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 41.78 MHz
41.78 MHz PLL with programmable divider
126 kB Flash/EE memory, 32 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
Up to 16 ADC channels
4 DAC outputs available
REF
analog input range
CMP
XCLKO
ADC15
XCLKI
ADC0
CMP0
CMP1
V
RST
OUT
REF
AND PLL
PSM
POR
OSC
MUX
Precision Analog Microcontroller, 12-Bit Analog I/O, Large
12-BIT ADC
BAND GAP
PURPOSE TIMERS
SENSOR
1MSPS
TEMP
PLA
FUNCTIONAL BLOCK DIAGRAM
REF
4 GENERAL-
Memory, ARM7TDMI MCU with Enhanced IRQ Handler
63k × 16 FLASH/EEPROM
8k × 32 SRAM
ARM7TDMI-BASED MCU WITH
ADuC7124/ADuC7126
ADDITIONAL PERIPHERALS
SPI, 2 × I
CONTROLLER
Figure 1.
2 × UART
INTERRUPT
VECTORED
2
C,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
On-chip peripherals
Power
Packages and temperature range
Tools
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
Patient monitoring
2× fully I
SPI (20 MBPS in master mode, 10 MBPS in slave mode)
2× UART channels
Up to 40 GPIO port
4× general-purpose timers
Programmable logic array (PLA)
16-bit, 6-channel PWM
Power supply monitor
Specified for 3 V operation
Active mode: 11.6 mA at 5 MHz, 33.3 mA at 41.78 MHz
Fully specified for −40°C to +125°C operation
64-lead LFCSP and 80-lead LQFP
Low cost QuickStart development system
Full third-party support
JTAG
GPIO
With 4-byte FIFO on input and output stages
With 16-byte FIFO on input and output stages
All GPIOs are 5 V tolerant
Watchdog timer (WDT) and wake-up timer
16 PLA elements
2
PWM
C-compatible channels
12-BIT
12-BIT
12-BIT
12-BIT
DAC
DAC
DAC
DAC
ADuC7124/ADuC7126
©2010–2011 Analog Devices, Inc. All rights reserved.
INTERFACE
EXTERNAL
MEMORY
DAC0
DAC1
DAC2
DAC3
www.analog.com

Related parts for ADUC7124

ADUC7124 Summary of contents

Page 1

... PLA GPIO 63k × 16 FLASH/EEPROM 2 4 GENERAL- SPI, 2 × JTAG PURPOSE TIMERS 2 × UART Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADuC7124/ADuC7126 2 C-compatible channels 12-BIT DAC0 DAC 12-BIT DAC1 DAC 12-BIT DAC2 DAC 12-BIT DAC3 ...

Page 2

... ADuC7124/ADuC7126 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 13 ESD Caution ................................................................................ 13 Pin Configurations and Function Descriptions ......................... 14 Typical Performance Characteristics ........................................... 23 Terminology .................................................................................... 26 ADC Specifications .................................................................... 26 DAC Specifications..................................................................... 26 Overview of the ARM7TDMI Core ............................................. 27 Thumb Mode (T) ........................................................................ 27 Long Multiply (M) ...................................................................... 27 EmbeddedICE (I) ...

Page 3

... Added Figure 58 and Figure 59 ..................................................... 98 Added Figure 60 and Figure 61 ..................................................... 99 Changes to Figure 62 to Figure 65 .............................................. 100 Changes to Figure 67 and Figure 68 ........................................... 101 Change to Power-On Reset Operation Section and Figure 69 ......................................................................................... 102 Added Figure 71 ............................................................................ 103 Changes to Ordering Guide ......................................................... 104 9/10—Revision 0: Initial Version Rev Page 3 of 104 ADuC7124/ADuC7126 ...

Page 4

... The parts operate from 2 3.6 V and is specified over an industrial temperature range of −40°C to +125°C. When operat- ing at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7124 is available in a 64-lead LFCSP package. The ADuC7126 is available in a 80-lead LQFP package. Rev Page 4 of 104 ...

Page 5

... Bits ±2 LSB ±1 LSB 10 mV 1.0 % 0.1 % Rev Page 5 of 104 ADuC7124/ADuC7126 = −40°C to +125°C, unless otherwise noted. A Test Conditions/Comments Eight acquisition clocks and f /2 ADC 2.5 V internal reference 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input voltage kHz sine wave, f ...

Page 6

... DACxDAT register) Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register 100 mV overdrive and configured with CMPRES = 11 ADuC7124 ADuC7126 ADuC7124 ADuC7126 A single point calibration is required Two selectable trip points Of the selected nominal trip point voltage T = 85°C J ...

Page 7

... Rev Page 7 of 104 ADuC7124/ADuC7126 Test Conditions/Comments All logic inputs excluding XCLKI All digital outputs excluding XCLKO I = 1.6 mA SOURCE I = 1.6 mA SINK 85° 125°C A Core clock = 41.78 MHz ...

Page 8

... ADuC7124/ADuC7126 Parameter ESD TESTS HBM Passed Up To FICDM Passed All ADC channel specifications are guaranteed during normal core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). ...

Page 9

... DAV MSB BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 t DSU t DHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev Page 9 of 104 ADuC7124/ADuC7126 t R ACK MSB DHD RSU REPEATED START Typ Max (SPIDIV + 1) × ...

Page 10

... ADuC7124/ADuC7126 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge DOSU t Data input setup time before SCLOCK edge ...

Page 11

... DAV MSB BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 t DSU t DHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev Page 11 of 104 ADuC7124/ADuC7126 Typ Max (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK 25 UCLK UCLK 5 12.5 5 12.5 5 12.5 5 12.5 t SFS ...

Page 12

... ADuC7124/ADuC7126 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...

Page 13

... Only one absolute maximum rating can be applied at any one time. −0 +5.3 V ESD CAUTION −0 IOV + 0 −0 0 −0 0 −0 0 –40°C to +125°C −65°C to +150°C 150°C 24°C/W 38°C/W 240°C 260°C Rev Page 13 of 104 ADuC7124/ADuC7126 ...

Page 14

... DAC1/ADC13 TMS TDI XCLKO XCLKI BM/P0.0/CMP /PLAI[7] OUT CONNECT NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Table 9. Pin Function Descriptions (ADuC7124 64-Lead LFCSP) Pin No. Mnemonic 0 Exposed Paddle 1 ADC4 2 ADC5 3 ADC6 4 ...

Page 15

... Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. Multifunction I/O Pin. Boot mode (BM). The ADuC7124 enters download mode low at reset and executes code pulled high at reset through a 1 kΩ resistor. General-Purpose Input and Output Port 0.0 (P0.0). ...

Page 16

... ADuC7124/ADuC7126 Pin No. Mnemonic 35 IRQ1/P0.5/ADC /PLAO[2] BUSY 36 P2.0/SPM9/PLAO[5]/CONV START 37 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 38 IOGND 39 IOV DD 40 P3.6/PWM /PLAI[14] TRIP 41 P3.7/PWM /PLAI[15] SYNC 42 P1.7/SPM7/DTR/SPICS /PLAO[0] 43 P1.6/SPM6/PLAI[6] 44 P4.0/PLAO[8]/SIN1 45 P4.1/PLAO[9]/SOUT1 46 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 47 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 48 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] 49 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] Description Multifunction I/O Pin. External Interrupt Request 1, Active High (IRQ1). ...

Page 17

... Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2 (ADC2). Comparator Positive Input (CMP0). Single-Ended or Differential Analog Input 3 (ADC3). Comparator Negative Input (CMP1). Rev Page 17 of 104 ADuC7124/ADuC7126 . DD ...

Page 18

... ADuC7124/ADuC7126 ADC4 1 ADC5 2 ADC6 3 ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADCNEG 8 DACGND 9 DACV 10 DD DAC0/ADC12 11 DAC1/ADC13 12 DAC2/ADC14 13 DAC3/ADC15 14 TMS 15 TDI 16 P0.1/PWM4/BLE 17 XCLKO 18 XCLKI 19 BM/P0.0/CMP /PLAI[7]/MS0 20 OUT Table 10 ...

Page 19

... External Memory Interface (AD1). PWM Phase 1 (PWM1). Programmable Logic Array Input Element 9 (PLAI[9]). General-Purpose Input and Output Port 3.2 (P3.2). External Memory Interface (AD2). PWM Phase 2 (PWM2). Programmable Logic Array Input Element 10 (PLAI[10]). Rev Page 19 of 104 ADuC7124/ADuC7126 2 C version parts low at reset with a ). OUT ...

Page 20

... ADuC7124/ADuC7126 Pin No. Mnemonic 34 P3.3/AD3/PWM3/PLAI[11] 35 P2.4/SPM13/PWM0/MS0/SOUT1 36 P0.3/TRST/A16/ADC BUSY 37 P2.5/PWM1/MS1 38 P2.6/PWM2/MS2 39 P3.4/AD4/PWM4/PLAI[12] 40 P3.5/AD5/PWM5/PLAI[13] 41 RST 42 IRQ0/P0.4/PWM /PLAO[1]/MS1 TRIP 43 IRQ1/P0.5/ADC /PLAO[2]/MS2 BUSY 44 P2.7/PWM3/MS3 45 P2.0/SPM9/PLAO[5]/ CONV START 46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0 47 IOGND 48 IOV DD Description General-Purpose Input and Output Port 3.3 (P3.3). External Memory Interface (AD3). PWM Phase 3 (PWM3). ...

Page 21

... General-Purpose Input and Output Port 1.3 (P1.3). Serial Port Multiplexed (SPM3). Clear to Send (CTS). I2C1 (I2C1SDA). Programmable Logic Array Input Element 3 (PLAI[3]). General-Purpose Input and Output Port 1.2 (P1.2). Serial Port Multiplexed (SPM2). Ready to Send (RTS). I2C1 (I2C1SCL). Programmable Logic Array Input Element 2 (PLAI[2]). Rev Page 21 of 104 ADuC7124/ADuC7126 ...

Page 22

... ADuC7124/ADuC7126 Pin No. Mnemonic 62 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] 63 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] 64 P4.2/AD10/PLAO[10] 65 P4.3/AD11/PLAO[11] 66 P4.4/AD12/PLAO[12] 67 P4.5/AD13/PLAO[13]/RTCK 68 IOV DD 69 IOGND 70 V REF 71 DAC REF 73, 74 AGND 75 GND REF 76 ADC11 77 ADC0 78 ADC1 79 ADC2/CMP0 80 ADC3/CMP1 Description General-Purpose Input and Output Port 1.1 (P1.1). Serial Port Multiplexed (SPM1). UART0 Output (SOUT0). I2C0 (I2C0SDA). ...

Page 23

... Figure 12. Typical INL Error, Temperature 25°C, V REF ADCCP = DAC1/ADC13, ADCCN = ADC0, Sampling Rate = 345 kHz Worst Case Positive = 0.58 LSB, Code 480 Worst Case Negative= −0.54 LSB, Code 3614 Rev Page 23 of 104 ADuC7124/ADuC7126 ADC CODES = Internal 2.5 V, Single-Ended Mode ADC CODES = Internal 2.5 V, Single-Ended Mode ...

Page 24

... ADuC7124/ADuC7126 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 ADC CODES Figure 13. Typical DNL Error, Temperature 25° Internal 2.5 V, Single-Ended Mode REF ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz Worst-Case Positive = 0.42 LSB, Code 3583 Worst-Case Negative = −0.32 LSB, Code 3073 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 ADC CODES Figure 14. Typical INL Error, Temperature 25° ...

Page 25

... DAC0 Max Positive INL: 1.84106, DAC1 Max Positive INL: 1.75312 DAC0 Max Negative INL: −0.887319, DAC1 Max Negative INL: −2.23708 Rev Page 25 of 104 ADuC7124/ADuC7126 50 100 150 FREQUENCY (kHz) = Internal 2.5 V, Single-Ended Mode REF DAC0 ...

Page 26

... ADuC7124/ADuC7126 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ ...

Page 27

... R11 R12_FIQ R12 R13_FIQ R13 R14_FIQ R14 R15 (PC) CPSR SPSR_FIQ FIQ USER MODE MODE Figure 23. Register Organization Rev Page 27 of 104 ADuC7124/ADuC7126 USABLE IN USER MODE SYSTEM MODES ONLY R13_UND R13_IRQ R13_ABT R14_UND R14_IRQ R13_SVC R14_ABT R14_SVC SPSR_UND SPSR_IRQ SPSR_ABT SPSR_SVC SVC ...

Page 28

... ADuC7124/ADuC7126 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in the following materials from ARM: • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: • ...

Page 29

... Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7124/ADuC7126 are on the APB except the Flash/EE memory and the GPIOs. Rev Page 29 of 104 ...

Page 30

... ADuC7124/ADuC7126 0xFFFFFFFF FLASH CONTROL INTERFACE 1 0xFFFFF880 FLASH CONTROL INTERFACE 0 0xFFFFF800 GPIO 0xFFFFF400 EXTERNAL MEMORY 0xFFFFF000 PWM 0xFFFF0F80 PLA 0xFFFF0B00 SPI 0xFFFF0A00 I2C1 0xFFFF0900 I2C0 0xFFFF0800 UART1 0xFFFF0740 UART0 0xFFFF0700 DAC 0xFFFF0600 ADC 0xFFFF0500 BAND GAP REFERENCE 0xFFFF048C POWER SUPPLY MONITOR 0xFFFF0440 ...

Page 31

... RSTCFG 1 RSTKEY1 1 Name Byte T0LD 2 T0VAL 2 T0CON 2 T0CLRI 1 T1LD 4 T1VAL 4 T1CON 2 T1CLRI 1 T1CAP 4 T2LD 4 T2VAL 4 T2CON 2 T2CLRI 1 T3LD 2 T3VAL 2 T3CON 2 T3CLRI 1 Rev Page 31 of 104 ADuC7124/ADuC7126 Access Type R/W R R/W R/W R/W R/W R/W R R/W Access Type R R/W W Access Type R/W R R/W W R/W R R/W W R/W R/W R ...

Page 32

... ADuC7124/ADuC7126 Table 14. PLL/PSM Base Address = 0xFFFF0400 Address 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF0434 0xFFFF0438 0xFFFF043C Table 15. PSM Base Address = 0xFFFF0440 Address 0xFFFF0440 0xFFFF0444 Table 16. Reference Base Address = 0xFFFF0480 Address 0xFFFF048C Table 17. ADC Base Address = 0xFFFF0500 Address 0xFFFF0500 0xFFFF0504 0xFFFF0508 0xFFFF050C ...

Page 33

... Byte Access Type 2 R R R/W 1 R/W 2 R R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev Page 33 of 104 ADuC7124/ADuC7126 Cycle Cycle Cycle ...

Page 34

... ADuC7124/ADuC7126 Table 22. I2C1 Base Address = 0xFFFF0900 Address Name 0xFFFF0900 I2C1MCON 0xFFFF0904 I2C1MSTA 0xFFFF0908 I2C1MRX 0xFFFF090C I2C1MTX 0xFFFF0910 I2C1MCNT0 0xFFFF0914 I2C1MCNT1 0xFFFF0918 I2C1ADR0 0xFFFF091C I2C1ADR1 0xFFFF0924 I2C1DIV 0xFFFF0928 I2C1SCON 0xFFFF092C I2C1SSTA 0xFFFF0930 I2C1SRX 0xFFFF0934 I2C1STX 0xFFFF0938 I2C1ALT 0xFFFF093C I2C1ID0 0xFFFF0940 I2C1ID1 0xFFFF0944 ...

Page 35

... XM1PAR 0xFFFFF028 XM2PAR 0xFFFFF02C XM3PAR Byte Access Type 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 R Byte Access Type 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 2 R/W 2 R/W 2 R/W 2 R/W Rev Page 35 of 104 ADuC7124/ADuC7126 Cycle Cycle ...

Page 36

... ADuC7124/ADuC7126 Table 27. GPIO Base Address = 0xFFFF0400 Address Name 0xFFFFF400 GP0CON 0xFFFFF404 GP1CON 0xFFFFF408 GP2CON 0xFFFFF40C GP3CON 0xFFFFF410 GP4CON 0xFFFFF420 GP0DAT 0xFFFFF424 GP0SET 0xFFFFF428 GP0CLR 0xFFFFF42C GP0PAR 0xFFFFF430 GP1DAT 0xFFFFF434 GP1SET 0xFFFFF438 GP1CLR 0xFFFFF43C GP1PAR 0xFFFFF440 GP2DAT 0xFFFFF444 GP2SET 0xFFFFF448 GP2CLR 0xFFFFF44C ...

Page 37

... Rev Page 37 of 104 ADuC7124/ADuC7126 FULL- SCALE 1LSB = 4096 0V 1LSB +FS – 1LSB VOLTAGE INPUT and V ...

Page 38

... ADuC7124/ADuC7126 TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits. The 12-bit result is placed in Bit 16 to Bit 27 as shown in Figure 30. Again, it should be noted that in fully differential mode, the result is represented in twos complement format ...

Page 39

... ADC interrupt cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADC pin. This pin is high during a conversion. When the conversion is finished, ADC BUSY Rev Page 39 of 104 ADuC7124/ADuC7126 ADCCN 0xFFFF0508 0x01 Read/write ADCSTA 0xFFFF050C ...

Page 40

... B V REF Figure 33. ADC Conversion Phase Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the ADCNEG pin of the ADuC7124/ADuC7126. In Figure 34, ADCNEG is represented as V (Channel−) and The ADCNEG pin must be connected REF to ground low voltage. The input signal on V ...

Page 41

... CM 2.05 V 2.276 V 2.55 V 1.75 V 1.976 V 2.25 V Rev Page 41 of 104 ADuC7124/ADuC7126 ADuC7124/ ADuC7126 10Ω ADC0 0.01µF Figure 37. Buffering Single-Ended/Pseudo Differential Input ADuC7124/ ADuC7126 ADC0 V REF ADC1 Figure 38. Buffering Differential Inputs ), which is dependent upon CM minimum and V maximum values Signal Peak-to-Peak 2.5 V 2.048 V 1 ...

Page 42

... T = 25°C and 1415 mV for the ADuC7124 and 1392 mV for the ADuC7126 for every part. For some users not possible to obtain such a known pair. For such cases, the ADuC7124/ADuC7126 comes with a single point calibration value loaded in the TEMPREF register ...

Page 43

... REFCON, described in Table 36. Table 36. REFCON MMR Bit Descriptions Bit [7: connect an external reference source to the ADuC7124/ pin. When using ADuC7126, configure REFCON = 0x00. ADC and the DACs REF can be configured to use same or a different reference resource (see Table 66). Rev Page 43 of 104 ...

Page 44

... Flash/EE Memory The ADuC7124/ADuC7126 contain two 64 kB arrays of Flash/EE memory. In the first block, the lower available to the user, and the upper this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download ...

Page 45

... To access the part via the JTAG interface, the P0.0/BM pin must be set high. When debugging, user code should not write to the P0.1, P0.2, and P0.3 pins. If user code toggles any of these pins, JTAG debug pods are not able to connect to the ADuC7124/ADuC7126. If this happens, mass erase the part using the UART/I downloader. FLASH/EE MEMORY SECURITY The 126 kB of Flash/EE memory available to the user can be read and write protected ...

Page 46

... ADuC7124/ADuC7126 Table 45. FEE1STA Register Name Address Default Value FEE1STA 0xFFFFF880 0x0000 Table 46. FEE1MOD Register Name Address Default Value FEE1MOD 0xFFFFF884 0x80 Table 47. FEE1CON Register Name Address Default Value FEE1CON 0xFFFFF888 0x00 Table 48. FEE1DAT Register Name Address Default Value FEE1DAT 0xFFFFF88C 0xXXXX FEE1DAT is a 16-bit data register ...

Page 47

... This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. 0x0D Reserved Reserved. 0x0E Reserved Reserved. 0x0F Ping No operation, interrupt generated. 1 The FEExCON register always reads 0x07 immediately after execution of any of these commands. Rev Page 47 of 104 ADuC7124/ADuC7126 ...

Page 48

... ADuC7124/ADuC7126 Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions Bit Description 31 Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. [30:0] Write protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 0 to Page 3. Cleared by the user to protect the pages in writing. ...

Page 49

... Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000. Remap Operation When a reset occurs on the ADuC7124/ADuC7126, execution automatically starts in factory programmed, internal configuration code. This kernel is hidden and cannot be accessed by user code. If the part is in normal mode (BM pin is high), it ...

Page 50

... ADuC7124/ADuC7126 RSTKEY0 Register Name: RSTKEY0 Address: 0xFFFF0248 Default Value: N/A Access Write only RSTKEY1 Register Name: RSTKEY1 Address: 0xFFFF0250 Default Value: N/A Access: Write only Rev Page 50 of 104 ...

Page 51

... OTHER ANALOG PERIPHERALS DAC The ADuC7124/ADuC7126 incorporate two, or four, 12-bit voltage output DACs on chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ranges band gap 2.5 V reference DAC ...

Page 52

... Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 42 becomes worse as a function of output loading. Most of the ADuC7124/ADuC7126 data sheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 42 become larger ...

Page 53

... DD supply pin DD COMPARATOR The ADuC7124/ADuC7126 integrate a voltage comparator. The positive input is multiplexed with ADC2, and the negative input has two options: ADC3 or DAC0. The output of the comparator can be configured to generate a system interrupt, be routed directly to the programmable logic array, start an ADC conver- ...

Page 54

... OSCILLATOR AND PLL—POWER CONTROL Clocking System The ADuC7124/ADuC7126 integrate a 32.768 kHz ± 3% oscilla- tor, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency or at binary submultiples of it ...

Page 55

... POWCON0 = 0x27; Set core into nap mode POWKEY2 = 0xF4; Power Control System A choice of operating modes is available on the ADuC7124/ ADuC7126. Table 70 describes what part is powered on in the different modes and indicates the power-up time. Table 71 gives some typical values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits ...

Page 56

... ADuC7124/ADuC7126 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 73), and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and the power-down mode, and POWCON1 controls the clock ...

Page 57

... MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. Clearing this bit powers down I2C1. I2C0 block driving clock divider bits. 41.78 MHz. 10.44 MHz. 5.22 MHz. 1.31 MHz. Clearing this bit powers down I2C0. I2C1 block driving clock divider bits. 41.78 MHz. 10.44 MHz. 5.22 MHz. 1.31 MHz. Rev Page 57 of 104 ADuC7124/ADuC7126 ...

Page 58

... GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7124/ADuC7126 enter a power-saving mode, the GPIO pins retain their state. Also, note that, by setting RSTCFG Bit 0, the GPIO pins can retain their state during a watchdog or software reset ...

Page 59

... MEDIUM DRIVE STRENGTH 0.3 LOW DRIVE STRENGTH 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –24 –18 Figure 47. Programmable Strength for Low Level Rev Page 59 of 104 ADuC7124/ADuC7126 Description Medium drive strength. Low drive strength. High drive strength. –12 – SINK/SOURCE CURRENT (mA) –12 –6 ...

Page 60

... CPU. The ADuC7124/ADuC7126 has been equipped with two industry standard 16,450 type UARTs (UART0 and UART1). Each UART features a fractional divider that facilitates high accu- racy baud rate generation and is equipped with a 16-byte FIFO for the transmitter and a 16-byte FIFO for the receiver ...

Page 61

... COM0RX, and COM0DIV0 share the same address location.   COM0TX and COM0RX can be accessed when Bit 7 in the  COM0CON0 register is cleared. COM0DIV0 can be accessed when Bit 7 of COM0CON0 is set. Rev Page 61 of 104 ADuC7124/ADuC7126 COM0TX 0xFFFF0700 0x00 Read/write COM1TX 0xFFFF0740 0x00 ...

Page 62

... ADuC7124/ADuC7126 COM1DIV0 Register Name: COM1DIV0 Address: 0xFFFF0740 Default Value: 0x00 Access: Read/write COM1DIV0 is a low byte divisor latch for UART1. COM1TX, COM1RX, and COM1DIV0 share the same address location. COM1TX and COM1RX can be accessed when Bit 7 in COM1CON0 register is cleared. COM1DIV0 can be accessed when Bit 7 of COM1CON0 is set ...

Page 63

... FIFOEN COM0CON0 Register Name: Address: Default Value: Access: COM0CON0 is the line control register for UART0. Rev Page 63 of 104 ADuC7124/ADuC7126 COM1FCR 0xFFFF0748 0x00 Read/write Description Receiver FIFO trigger level. RXFIFOTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled) ...

Page 64

... ADuC7124/ADuC7126 COM1CON0 Register Name: COM1CON0 Address: 0xFFFF074C Default Value: 0x00 Access: Read/write COM1CON0 is the line control register for UART1. Table 95. COMxCON0 MMR Bit Descriptions Bit Name Description 7 DLAB Divisor latch access. Set by the user to enable access to the COMxDIV0 and COMxDIV1 registers. ...

Page 65

... Delta DSR. Set automatically if DSR changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. 0 DCTS Delta CTS. Set automatically if CTS changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Rev Page 65 of 104 ADuC7124/ADuC7126 COM0STA1 0xFFFF0718 0x00 Read only COM1STA1 0xFFFF0758 0x00 Read only ...

Page 66

... Configuring External Pins for SPI functionality The SPI pins of the ADuC7124/ADuC7126 device are P1.4 to P1.7. . P1.7 is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer ...

Page 67

... FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA. Rev Page 67 of 104 ADuC7124/ADuC7126 ...

Page 68

... ADuC7124/ADuC7126 SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is the SPI receive register. SPITX Register Name: SPITX Address: 0xFFFF0A08 Default Value: 0x00 Access: Write only Function: This 8-bit MMR is the SPI transmit register. ...

Page 69

... Cleared by the user, the serial clock pulses at the end of each serial bit transfer. 1 SPIMEN Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI. Rev Page 69 of 104 ADuC7124/ADuC7126 ...

Page 70

... I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b. Rev Page 70 of 104 2 C Functionality 2 C pins of the ADuC7124/ADuC7126 device are P1.0 and 2 C clock signals, and P1.1 and P1.3 are C data signals. For instance, to configure I2C0 pins (SCL0 mode. On the other hand, to configure I2C1 pins ...

Page 71

... C master receives a NACK master is unable to gain control of the master has transmitted a byte master receives data master is receiving data bus becomes free master mode master mode. Rev Page 71 of 104 ADuC7124/ADuC7126 2 C peripheral bus bus. ...

Page 72

... ADuC7124/ADuC7126 Master Status Register Name: I2C0MSTA, I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I Table 103. I2CxMSTA MMR Bit Descriptions Bit Name Description [15:11] Reserved I2CBBUSY I C bus busy status bit. This bit is set to 1 when a start condition is detected on the I This bit is cleared when a stop condition is detected on the bus ...

Page 73

... Bit [7:1] 0 Table 106. I2CxADR0 MMR in 10-Bit Address Mode Bit [7:3] [2:1] 0 Rev Page 73 of 104 ADuC7124/ADuC7126 I2C0MCNT1, I2C1MCNT1 0xFFFF0814, 0xFFFF0914 0x00, 0x00 Read only This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device. I2C0ADR0, I2C1ADR0 0xFFFF0818, 0xFFFF0918 ...

Page 74

... ADuC7124/ADuC7126 Address 1 Register Name: I2C0ADR1, I2C1ADR1 Address: 0xFFFF081C, 0xFFFF091C Default Value: 0x00 Access: Read/write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Table 107. I2CxADR1 MMR in 10-Bit Address Mode Bit ...

Page 75

... This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7124/ ADuC7126 watch for these addresses. The device that requires attention embeds its own address into the message ...

Page 76

... ADuC7124/ADuC7126 Bit Name Description 2 [12:11] I2CID[1: address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3 I2CSS I C stop condition after start detected bit. ...

Page 77

... C slave transmit register. [7:6] [5:4] [3:2] [1: Rev Page 77 of 104 ADuC7124/ADuC7126 I2C0FSTA, I2C1FSTA 0xFFFF084C, 0xFFFF094C 0x0000 Read/write These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes. Name Description Reserved. I2CFMTX Set this bit flush the master Tx FIFO ...

Page 78

... ADuC7124/ADuC7126 PWM GENERAL OVERVIEW The ADuC7124/ADuC7126 integrate a 6-channel PWM interface (PWM0 to PWM5). The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins ...

Page 79

... Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs H-bridge mode, HMODE = 1. See Table 114 to determine the PWM outputs. pin. SYNC pin. SYNC 1 Rev Page 79 of 104 ADuC7124/ADuC7126 or Pin P0.4/PWM ) TRIP TRIP ...

Page 80

... ADuC7124/ADuC7126 Table 114. PWM Output Selection, HMODE = 1 1 PWMCON0 MMR ENA HOFF POINV DIR PWM0 PWM1 don’t care high side low side. ...

Page 81

... Figure 51. PLA Element In total, 40 GPIO pins are available on the ADuC7124/ADuC7126 for the PLA. These include 16 input pins and 16 output pins that must be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. ...

Page 82

... ADuC7124/ADuC7126 PLACLK Register Name: PLACLK Address: 0xFFFF0B40 Default Value: 0x00 Access: Read/write PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 120. PLACLK MMR Bit Descriptions ...

Page 83

... Access: Write only PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modification of any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Rev Page 83 of 104 ADuC7124/ADuC7126 ...

Page 84

... ADuC7124/ADuC7126 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 25 interrupt sources on the ADuC7124/ADuC7126 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ) ...

Page 85

... In the interrupt sources interrupt service routine. • The peripheral is temporarily disabled by its own control register. This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or may have an interrupt pending. Rev Page 85 of 104 ADuC7124/ADuC7126 ...

Page 86

... UNUSED (IRQBASE) Figure 52. Interrupt Structure VECTORED INTERRUPT CONTROLLER (VIC) The ADUC7124/ADuC7126 incorporate an enhanced interrupt control system or (vectored interrupt controller). The vectored interrupt controller for IRQ interrupt sources is enabled by set- ting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources ...

Page 87

... PLL lock interrupt. 11 Reserved. [10:8] UART1PI A priority level can be set for UART1. 7 Reserved. [6:4] UART0PI A priority level can be set for UART0. 5 Reserved. [2:0] ADCPI A priority level can be set for the ADC interrupt source. Rev Page 87 of 104 ADuC7124/ADuC7126 ...

Page 88

... ADuC7124/ADuC7126 IRQP2 Register Name: IRQP2 Address: 0xFFFF0028 Default Value: 0x00000000 Access: Read/write Table 132. IRQP2 MMR Bit Descriptions Bit Name Description 31 Reserved. [30:28] IRQ3PI A priority level can be set for IRQ3. 27 Reserved. [26:24] IRQ2PI A priority level can be set for IRQ2. ...

Page 89

... Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. External Interrupts and PLA interrupts The ADuC7124/ADuC7126 provide up to four external interrupt sources and two PLA interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. ...

Page 90

... ADuC7124/ADuC7126 Bit Value Name [7:6] 11 IRQ2SRC[1: [5:4] 11 PLA0SRC[1: [3:2] 11 IRQ1SRC[1: [1:0] 11 IRQ0SRC[1: IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default Value: 0x00000000 Access: Write only Table 139. IRQCLRE MMR Bit Descriptions Bit Name [31:25] 24 PLA1CLRI 23 IRQ3CLRI 22 IRQ2CLRI 21 PLA0CLRI 20 IRQ1CLRI [19:18] 17 IRQ0CLRI ...

Page 91

... TIMERS The ADuC7124/ADuC7126 have four general-purpose timers/counters. • Timer0 • Timer1 • Timer2 or wake-up timer • Timer3 or watchdog timer These four timers in their normal mode of operation can be either free running or periodic. In free-running mode, the counter decreases from the maxi- mum value until zero scale is reached and starts again at the minimum value ...

Page 92

... ADuC7124/ADuC7126 Table 140. T0CON MMR Bit Descriptions Bit Value Description [31:8] Reserved. 7 Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 by default. 6 Timer0 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode. Default mode. ...

Page 93

... Address: Default Value: Access: This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2. Rev Page 93 of 104 ADuC7124/ADuC7126 Read/write Description 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer2 interrupt ...

Page 94

... ADuC7124/ADuC7126 Timer2 Value Register Name: T2VAL Address: 0xFFFF0344 Default Value: 0x0000 Access: Read only T2VAL is a 32-bit register that holds the current value of Timer2. Table 143. T2CON MMR Bit Descriptions Bit Value Description [31:11] Reserved. 10:9] Clock source select. 00 External 32.768 kHz watch crystal (default). ...

Page 95

... Bit Value [31: [3: Rev Page 95 of 104 ADuC7124/ADuC7126 T3VAL 0xFFFF0364 0xFFFF Read only T3CON 0xFFFF0368 0x0000 Read/write Description Reserved. Count up. Set by the user for Timer3 to count up. Cleared by the user for Timer3 to count down by default. Timer3 enable bit. ...

Page 96

... Enter 0x6E in T3CLRI; Timer3 is reloaded. 5. Enter 0x66. 0xDC was expected; the watchdog resets the chip. EXTERNAL MEMORY INTERFACING The ADuC7124/ADuC7126 feature an external memory interface. The external memory interface requires a larger number of pins. The XMCFG MMR must be set use the external port. ...

Page 97

... Figure 58, Figure 59, Figure 60, and Figure 61 show the timing Access for a read cycle, a read cycle with address hold and bus turn R/W cycles, a write cycle with address and write hold cycles, and a R/W write cycle with wait sates, respectively. R/W R/W Rev Page 97 of 104 ADuC7124/ADuC7126 signals. BHE and BLE signals. ...

Page 98

... ADuC7124/ADuC7126 MCLK AD[15:0] MSx AE RS MCLK AD[15:0] MSx AE RS Figure 59. External Memory Read Cycle with Address Hold and Bus Turn Cycles ADDRESS Figure 58. External Memory Read Cycle ADDRESS EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) BUS TURN OUT CYCLE (BIT 9) Rev Page 98 of 104 ...

Page 99

... AD[15:0] ADDRESS MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) WS Figure 61. External Memory Write Cycle with Wait States Rev Page 99 of 104 ADuC7124/ADuC7126 DATA WRITE HOLD ADDRESS WRITE HOLD ADDRESS AND DATA CYCLES AND DATA CYCLES (BIT 8) (BIT 8) DATA 1 WRITE STROBE WAIT STATE ...

Page 100

... IOV recommended. 0.1µF and then decoupling DD Linear Voltage Regulator The ADuC7124/ADuC7126 require a single 3.3 V supply, but ANALOG SUPPLY the core logic requires a 2.6 V supply. An on-chip linear regulator generates the 2.6 V from IOV 10µF LV pin is the 2.6 V supply for the core logic. An external DD compensation capacitor of 0.47 µ ...

Page 101

... When connecting fast logic signals (rise/fall time < 5 ns) to any of the ADuC7124/ADuC7126 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the input pins of the part. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capaci- tively into the part and affecting the accuracy of ADC conversions ...

Page 102

... ADuC7124/ADuC7126 POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7124/ADuC7126. For LV below 2.40 V typical, the DD internal POR holds the part in reset internal timer times out for typically 128 ms before the part is released from reset. The user must ensure that the power supply, IOV , reaches a stable 2 ...

Page 103

... COPLANARITY VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BDD Figure 71. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters Rev Page 103 of 104 ADuC7124/ADuC7126 0.30 0.25 0.18 PIN 1 64 INDICATOR 1 * 4.85 EXPOSED PAD 4.70 SQ (BOTTOM VIEW) 4. 7.50 REF FOR PROPER CONNECTION OF ...

Page 104

... LFCSP_VQ −40°C to 80-Lead LQFP ST-80-1 +125°C −40°C to 80-Lead LQFP ST-80-1 +125°C −40°C to 80-Lead LQFP ST-80-1 +125°C −40°C to 80-Lead LQFP ST-80-1 +125°C ADuC7124 QuickStart Development System ADuC7126 QuickStart Development System Ordering Quantity 260 2500 119 1000 119 1000 ...

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