ADUC7122 Analog Devices, ADUC7122 Datasheet

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ADUC7122

Manufacturer Part Number
ADUC7122
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7122

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
32
Adc # Channels
13
FEATURES
Analog I/O
Microcontroller
Clocking options
Memory
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
13-external channel, 12-bit, 1 MSPS ADC
Fully differential and single-ended modes
0 V to V
12 × 12-bit voltage output DACs
On-chip voltage reference: 1.2 V/2.5 V
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 41.78 MHz
41.78 MHz PLL with programmable divider
126 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Buffered output reference sources for use with external
2 differential channels with programmable gain
IOVDD power monitor channel
On-chip temperature monitor
11 general-purpose inputs
PGA (1 to 5) input range
circuits
REF
PADC0
PADC1
ADC10
analog input range
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
TEMPERATURE
REFERENCE
INTERNAL
SENSOR
PGA
PGA
V
REF
IOVDD MON
AVDD 3.3V AGND
_1.2
BUF
V
REF
_2.5
FUNCTIONAL BLOCK DIAGRAM
DAC0
Precision Analog Microcontroller, 12-Bit
P0.0 TO P0.7
SAR ADC
1MSPS
12-BIT
ADuC7122
DAC1
DAC2
Figure 1.
DAC3
P1.0 TO P1.7
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
On-chip peripherals
Vectored interrupt controller for FIQ and IRQ
Power
Packages and temperature range
Tools
APPLICATIONS
Optical networking, industrial control, and automation
Smart sensors and precision instrumentation
DAC4 DAC5
Software-triggered in-circuit reprogrammability
UART, 2× I
32-pin GPIO port
4 general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz
7 mm × 7 mm 108-ball BGA
Fully specified for −10°C to +95°C operation
Low cost QuickStart development system
Full third-party support
systems
WAKE-UP
TIMER
TIMER
Analog I/O, ARM7TDMI MCU
JTAG
OSC
WD
VIC
P2.0 TO P2.7
DAC6
2
CONTROL
C and SPI serial I/Os
TIMERS
FLASH
16-BIT)
(63k ×
3× GP
126k
PLL
GPIO
DAC7 DAC8
PLA
(2k × 32-BIT)
8k SRAM
©2010 Analog Devices, Inc. All rights reserved.
ARM7
TDMI
POR
SPI
P3.0 TO P3.7
DAC
DAC
DAC
1
UART
PWM
2
LDO
C × 2
BUF
BUF
BUF
ADuC7122
DAC9
DAC10
DAC11
IOVDD
IOGND
XTALI
XTALO
RST
TDO
TDI
TCK
TMS
TRST
www.analog.com

Related parts for ADUC7122

ADUC7122 Summary of contents

Page 1

... SAR ADC WAKE-UP TIMER ADuC7122 V _2.5 REF P0.0 TO P0.7 P1.0 TO P1.7 Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Analog I/O, ARM7TDMI MCU ADuC7122 2 C and SPI serial I/Os DAC6 DAC7 DAC8 DAC BUF DAC9 DAC BUF DAC10 DAC DAC11 BUF PLA ...

Page 2

... ADuC7122 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Terminology .................................................................................... 19 ADC Specifications .................................................................... 19 DAC Specifications..................................................................... 19 Overview of the ARM7TDMI Core ............................................. 20 Thumb Mode (T) ........................................................................ 20 Long Multiply (M) ...................................................................... 20 EmbeddedICE (I) ....................................................................... 20 Exceptions ...

Page 3

... REVISION HISTORY 4/10—Revision 0: Initial Version Rev Page ADuC7122 ...

Page 4

... ADuC7122 GENERAL DESCRIPTION The ADuC7122 is a fully integrated, 1 MSPS, 12-bit data acquisi- tion system, incorporating high performance multichannel ADCs, 12 voltage output DACs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists inputs. Four of these inputs can be configured as differential pairs with a programmable gain amplifier on their front end, providing a gain between 1 and 5 ...

Page 5

... AV − 1 Rev Page ADuC7122 = −10°C to +95°C, unless otherwise noted. A Test Conditions/Comments Eight acquisition clocks and f /2 ADC 2.5 V internal reference, not production tested for PADC0/PADC1 channels 2.5 V internal reference, gauranteed monotonic ADC input voltage Internally unbuffered channels ...

Page 6

... ADuC7122 Parameter ON-CHIP VOLTAGE REFERENCE Output Voltage 7 Accuracy 4 Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal V Power-On Time REF EXTERNAL REFERENCE INPUT Input Voltage Range BUF_VREF1, BUF_VREF2 OUTPUTS Accuracy Reference Temperature Coefficient Load Current DAC CHANNEL SPECIFICATIONS 8 DC Accuracy ...

Page 7

... Rev Page ADuC7122 Test Conditions/Comments T = 85°C J All digital inputs excluding XCLKI and XTALO except TDI IL All logic inputs excluding XTALI All digital outputs excluding XTALO ...

Page 8

... ADuC7122 Parameter ESD TESTS HBM Passed Up To FCIDM Passed All ADC channel specifications are guaranteed during normal MicroConverter core operation. 2 Applies to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN); see the the Calibration section. ...

Page 9

... SUP MSB LSB t DSU t DHD 2– Figure 2. I C-Compatible Interface Timing Rev Page ADuC7122 Slave Master Typ Max Min Typ 1360 1140 740 400 800 300 200 300 Slave Typ Max 3.45 1 300 t R ACK MSB ...

Page 10

... ADuC7122 Table 4. SPI Master Mode Timing (SPICPH = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...

Page 11

... UCLK 2 × t UCLK DAV MSB BITS MSB IN BITS DHD Figure 4. SPI Master Mode Timing (SPICPH = 0) Rev Page ADuC7122 Typ Max Unit (SPIDIV + 1) × UCLK (SPIDIV + 1) × UCLK 12 12.5 ...

Page 12

... ADuC7122 Table 6. SPI Slave Mode Timing (SPICPH = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...

Page 13

... UCLK DAV MSB BITS MSB IN BITS DHD Figure 6. SPI Slave Mode Timing (SPICPH = 0) Rev Page ADuC7122 Typ Max (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 25 5 12.5 5 12.5 5 12 SFS ...

Page 14

... ADuC7122 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GND unless otherwise noted. Table 8. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage to IOGND Digital Output Voltage to IOGND V _2.5 and V _1.2 to AGND REF REF Analog Inputs to AGND Analog Outputs to AGND ...

Page 15

... I C Interface SCLOCK for I2C1 (SCL2). Input to PLA Element 7 (PLAI[7]). I/O General-Purpose Input and Output Port 1.1 (P1.1). Serial Output, Transmit Data (TxD), UART (SOUT Interface SDATA for I2C1 (SDA2). Input to PLA Element 6 (PLAI[6]). Rev Page ADuC7122 ...

Page 16

... ADuC7122 Pin No. Mnemonic H3 P1.4/PWM1/PLAI[8]/ECLK/XCLK J3 P1.5/PWM2/PLAI[9] B3 P1.6/PLAO[5] B2 P1.7/PLAO[4] F11 P2.0/IRQ0/PLAI[13] G11 P2.1/IRQ1/PLAI[12] H11 P2.2/PLAI[1] J11 P2.3/IRQ2/PLAI[14] H10 P2.4/PWM5/PLAO[7] J10 P2.5/PWM6/PLAO[6] C1 P2.6/IRQ3/PLAI[15] C9 P2.7/PLAI[0] C4 P3.0/PLAO[0] C11 P3.1/PLAO[1] D1 P3.2/IRQ4/PWM3/PLAO[2] E1 P3.3/IRQ5/PWM4/PLAO[3] E2 P3.4/PLAO[8] F2 P3.5/PLAO[9] D12 P3.6/PLAO[10] 1 Type Description I/O General-Purpose Input and Output Port 1.4 (P1.4). PWM1 Output (PWM1). ...

Page 17

... DAC Output. AO 12-Bit DAC Output. AO 12-Bit DAC Output Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect Connect. Rev Page ADuC7122 ...

Page 18

... ADuC7122 Pin No. Mnemonic A9 NC A11 NC A10 NC B12 NC B11 NC B10 AGND B9 AGND M1 AGND M6 AGND L1 AVDD M7 AVDD M12 AGND B6 AGND L12 AVDD REG_PWR G1 LVDD G12 LVDD F1 DGND F12 DGND H1 IOVDD J1 IOGND H12 IOVDD J12 IOGND G2 XTALO H2 XTALI D10 TDO/P1.3/PLAO[14] C10 TDI/P1.2/PLAO[15] ...

Page 19

... DAC transfer function measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change. /2), excluding dc. S Rev Page ADuC7122 ...

Page 20

... ADuC7122 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits bits. The length of the instruction word is 32 bits. ...

Page 21

... Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged mode, for example, when executing interrupt service routines. Rev Page ADuC7122 ...

Page 22

... Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7122 are on the APB except the Flash/EE memory and the GPIOs. Rev Page ...

Page 23

... SPI 0x003C 0x0100 0x0104 I2C1 0x0108 0x010C I2C0 0x011C 0x013C Table 11. System Control Base Address = 0xFFFF0200 Address 0x0220 0x0230 0x0234 0x0248 0x024C 0x0250 Rev Page ADuC7122 Name Byte Access Type IRQSTA 4 R IRQSIG 4 R IRQEN 4 R/W IRQCLR 4 W SWICFG 4 W IRQBASE ...

Page 24

... ADuC7122 Table 12. Timer Base Address = 0xFFFF0300 Address Name Byte Access Type 0x0300 T0LD 2 R/W 0x0304 T0VAL0 2 R 0x0308 T0VAL1 4 R 0x030C T0CON 4 R/W 0x0310 T0CLRI 1 W 0x0314 T0CAP 2 R 0x0320 T1LD 4 R/W 0x0324 T1VAL 4 R 0x0328 T1CON 4 R/W 0x032C T1CLRI 1 W 0x0330 T1CAP 4 R 0x0340 ...

Page 25

... Cycle 0x094C Table 21. SPI Base Address = 0xFFFF0A00 2 Address 2 2 0x0A00 2 0x0A04 2 0x0A08 2 0x0A0C 2 0x0A10 Rev Page ADuC7122 Name Byte Access Type I2C1MCTL 2 R/W I2C1MSTA 2 R I2C1MRX 1 R I2C1MTX 2 R/W I2C1MCNT0 2 R/W I2C1MCNT1 1 R I2C1ADR0 1 R/W I2C1ADR1 1 R/W I2C1SBYTE 1 R/W ...

Page 26

... ADuC7122 Table 22. PLA Base Address = 0xFFFF0B00 Address Name Byte 0x0B00 PLAELM0 2 0x0B04 PLAELM1 2 0x0B08 PLAELM2 2 0x0B0C PLAELM3 2 0x0B10 PLAELM4 2 0x0B14 PLAELM5 2 0x0B18 PLAELM6 2 0x0B1C PLAELM7 2 0x0B20 PLAELM8 2 0x0B24 PLAELM9 2 0x0B28 PLAELM10 2 0x0B2C PLAELM11 2 0x0B30 PLAELM12 2 0x0B34 PLAELM13 2 0x0B38 PLAELM14 2 0x0B3C PLAELM15 ...

Page 27

... ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of 3C. For the ADuC7122, a number of modifications have been made when REF to the ADC input structure that appears in the ADuC702x family ...

Page 28

... ADC Input Channels The ADuC7122 provides 11 fixed gain ADC input pins. Each of these pins can be separately configured as a differential input pair, single-ended input, or positive side pseudo differential input (the negative side must be the AINCM channel). The buffer and ADC are configured independently from input channel selec- tion ...

Page 29

... When using multiple channels, including the temperature sensor, the timing settings revert back to the user- defined settings after reading the temperature sensor channel ADC CLOCK CONVST ADC BUSY ADCDAT Rev Page ADuC7122 ACQ BIT TRIAL WRITE DATA ADCSTA = 0 ADCSTA = 1 ADC INTERRUPT Figure 16. ADC Timing ...

Page 30

... ADuC7122 TEMPERATURE SENSOR The ADuC7122 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. ...

Page 31

... Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input. 011 Single software conversion. Automatically set to 000 after conversion. 100 Continuous software conversion. 101 PLA conversion. 110 Reserved Other Reserved conversion = 19 ADC clocks + acquisition time). CORE Rev Page ADuC7122 ...

Page 32

... ADuC7122 Table 29. ADCCP MMR Bit Designations (Address = 0xFFFF0504, Default Value = 0x00) Bit Value Description 7:5 Reserved 4:0 Positive channel selection bits 00000 PADC0P 00001 PADC1P 00010 ADC0 00011 ADC1 00100 ADC2 00101 ADC3 00110 ADC4 00111 ADC5 01000 ADC6 01001 ADC7 01010 ADC8 ...

Page 33

... ADC10 B V REF Figure 19. ADC Conversion Phase Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7122, and SW2 switches between A (Channel−) and B (V low voltage. The input signal REF does not exceed AV or PADCxN should be enabled for the V register is used to set Channel− ...

Page 34

... V 1.024 V 1.25 V 0.75 V BAND GAP REFERENCE The ADuC7122 provides an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This 2.5 V reference is generated from a 1.2 V reference. This internal reference also appears on the V V _2.5 pins. When using the internal reference, a 470 nF ...

Page 35

... PSMI Power supply monitor interrupt bit. This bit is set high by the ADuC7122 if CMP is low, indicating low I/O supply. The PSMI bit can be used to interrupt the processor. When CMP returns high, the PSMI bit can be cleared by writing this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately when CMP goes high ...

Page 36

... Figure 25. Flash/EE Memory Data Retention Serial Downloading (In-Circuit Programming) The ADuC7122 facilitates code download via the I port. The ADuC7122 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 kΩ resistor. This is combined with the state of Address 0x00014 in Flash. If this address is 0xFFFFFFFF and the BM pin is pulled low, the part enters download mode ...

Page 37

... Table 57). Command Sequence for Executing a Mass Erase FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; FEE0CON = 0x06; Rev Page ADuC7122 //Protect pages //Write key enable //16 bit key value //16 bit key value // Write key command Default Value Access ...

Page 38

... ADuC7122 Table 43. FEE1DAT Register Name Address Default Value FEE1DAT 0xFFFF0E8C 0xXXXX FEE1DAT is a 16-bit data register. Table 44. FEE1ADR Register Name Address Default Value FEE1ADR 0xFFFF0E90 0x0000 FEE1ADR is a 16-bit address register. Table 45. FEE1SGN Register Name Address Default Value FEE1SGN 0xFFFF0E98 0xFFFFFF FEE1SGN is a 24-bit code signature ...

Page 39

... Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEExSTA register. 0 Command complete. Set by ADuC7122 when a command is complete. Cleared automatically when reading the FEExSTA register. Table 55. FEExMOD MMR Bit Designations Bit Description 7:5 Reserved. Always set these bits to 0 except when writing Flash memory control keys. ...

Page 40

... ADuC7122 Table 57. FEE0PRO and FEE0HID MMR Bit Designations Bit Description 31 Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. 30:0 Write protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 3 to Page 0. Cleared by the user to protect the pages in writing. ...

Page 41

... Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. code. This kernel is hidden and cannot be accessed by user code. If the ADuC7122 is in normal mode (the BM pin is high), it executes the power-on configuration routine of the kernel and then jumps to the reset vector Address 0x00000000 to execute the reset exception routine of the user ...

Page 42

... ADuC7122 RSTCFG Register Name: RSTCFG Address: 0xFFFF024C Default value: 0x00 Access: Read/write Table 62. RSTCFG MMR Bit Designations Bit Description Reserved. Always set This bit is set configure the DAC outputs to retain their state after a watchdog or software reset. This bit is cleared for the DAC pins and registers to return to their default state ...

Page 43

... OTHER ANALOG PERIPHERALS DAC The ADuC7122 incorporates 12 buffered, 12-bit voltage output string DACs on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has two selectable ranges gap 2.5 V reference) and The maximum signal ...

Page 44

... ADuC7122 Table 65. DACxCON MMR Bit Designations Bit Value Name Description 15:9 0 Reserved DACPD DAC power-down. Set by user to set DACOUTx to tri-state mode Reserved BYP DAC bypass bit. Set this bit to bypass the DAC buffer. Cleared to buffer the DAC output DACCLK DAC update rate ...

Page 45

... LDO. The LVDD pin has no reverse battery, current limit, or thermal mode (with V < shutdown protection; therefore essential that users of the REF ADuC7122 do not short this pin to ground at anytime during normal operation or during board manufacture. Rev Page – ...

Page 46

... ADuC7122 OSCILLATOR AND PLL—POWER CONTROL The ADuC7122 integrates a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving. The default core clock is the PLL clock divided ...

Page 47

... POWER CONTROL SYSTEM A choice of operating modes is available on the ADuC7122. Table 68 describes which blocks of the ADuC7122 are powered on in the different modes and indicates the power-up time. Table 69 gives some typical values of the total current Table 68. Operating Modes Mode Core Peripherals Active ...

Page 48

... Reserved. External clock on P1.4 pin. Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7122. Stop mode. Reserved. Reserved. CPU clock divider bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. ...

Page 49

... DIGITAL PERIPHERALS PWM GENERAL OVERVIEW The ADuC7122 integrates a 6-channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the H-bridge controlled motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins ...

Page 50

... ADuC7122 Bit Name Description 8:6 PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. 000 = UCLK/2. 001 = UCLK/4. 010 = UCLK/8. 011 = UCLK/16. 100 = UCLK/32. 101 = UCLK/64. 110 = UCLK/128. 111 = UCLK/256. 5 POINV Set the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. ...

Page 51

... LOW SIDE COUNT TO CONVST Figure 33. ADC Conversion ADuC7122 ...

Page 52

... The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7122 parts enter a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 84 ...

Page 53

... GPIO Px.1 open-collector enable W Set the user to enable open-collector Set the user to disable open-collector W 0 GPIO Px.0 open-collector enable W Set the user to enable open-collector W Set the user to disable open-collector Rev Page ADuC7122 Default Value Access 0x000000XX W 0x000000XX W 0x000000XX W 0x000000XX W ...

Page 54

... BAUD RATE GENERATION The ADuC7122 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC7122 fractional divider. Normal 450 UART Baud Rate Generation The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL) ...

Page 55

... UART operates. Name: COMDIV1 Address: 0xFFFF0804 Default Value: 0x00 Access: Read/write UART Control Register 0 This 8-bit register controls the operation of the UART in conjunction with COMCON1. Name: COMCON0 Address: 0xFFFF080C Default Value: 0x00 Access: Read/write Rev Page ADuC7122 ...

Page 56

... ADuC7122 Table 95. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 STOP WLS UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: COMCON1 Address: 0xFFFF0810 Default Value: 0x00 Access: Read/write Description Divisor latch access. ...

Page 57

... Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data are overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. Rev Page ADuC7122 ...

Page 58

... UART Fractional Divider Register This 16-bit register controls the operation of the fractional divider for the ADuC7122. Name: COMDIV2 Address: 0xFFFF082C Default Value: 0x0000 Access: Read/write Table 100. COMDIV2 MMR Bit Designations Bit Name Description 15 FBEN Fractional baud rate generator enable bit ...

Page 59

... I2CxID0[7:1] = Address Bits[6:0]. I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b. Rev Page Functionality 2 C pins of the ADuC7122 device are P0.0 and P0.1 for 2 C clock signals, and P0.1 and P1.1 are C data signals. For instance, to configure the I2C0 pins 2 C mode. Alternatively, to configure the I2C1 2 C mode ...

Page 60

... ADuC7122 Master Mode In master mode, the I2CADR0 register is programmed with the address of the device. In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CADR0[7:3] must be set to 11110b. I2CADR0[2:1] = Address Bits[9:8]. ...

Page 61

... I C master Tx FIFO empty one byte in master Tx FIFO one byte in master Tx FIFO master Tx FIFO full status register in master mode master has lost in trying to gain control of the I Rev Page bus bus slave address. ADuC7122 ...

Page 62

... ADuC7122 Master Receive Register Name: I2C0MRX , I2C1MRX Address: 0xFFFF0888, 0xFFFF0908 Default Value: 0x00, 0x00 Access: Read only Function: This 8-bit MMR is the I register Master Transmit Register Name: I2C0MTX, I2C1MTX Address: 0xFFFF088C, 0xFFFF090C Default Value: 0x00, 0x00 Access: Read/write Function: This 8-bit MMR is the I register ...

Page 63

... This drives the byte written in I2CxSBYTE onto the bus fol- lowed by a repeated start. This register can be used to drive any 2 byte onto the I C bus followed by a repeated start (not a start byte only, for example, 00000001). Rev Page ADuC7122 section. ...

Page 64

... This is a broadcast message to all master devices on the bus. The ADuC7122 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. ...

Page 65

... C interface resets as per the January 2000 bus specification. This command can be used general call commands slave mode slave mode status register in slave mode. Rev Page general call, Address 0x00 (write). The device then ADuC7122 ...

Page 66

... ADuC7122 Bit Name Description 2 7 I2CGC I C general call status bit. This bit is set the slave receives a general call command of any type. If the command received is a reset command, then all registers return to their default state. If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxALT register ...

Page 67

... I C Slave Device ID Registers Name: Addresses slave receive Default Value: Access: Function slave transmit Rev Page ADuC7122 I2C0IDx, I2C1IDx 0xFFFF093C = I2C1ID0 0xFFFF08BC = I2C0ID0 0xFFFF0940 = I2C1ID1 0xFFFF08C0 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF08C4 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF08C8 = I2C0ID3 0x00 Read/write These 8-bit MMRs are programmed with I 2 bus IDs of the slave ...

Page 68

... ADuC7122 COMMON REGISTERS FIFO Status Register Name: I2C0FSTA, I2C1FSTA Address: 0xFFFF08CC, 0xFFFF094C Default Value: 0x0000 Access: Read/write Function: These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes. Table 110. I2CxFSTA MMR Bit Designations Bit Name ...

Page 69

... CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY The SPI pins of the ADuC7122 device are P0.2 to P0.5. P0.5 is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer ...

Page 70

... ADuC7122 SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. Table 111. SPISTA MMR Bit Designations Bit Name Description 15:12 Reserved bits. 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON ...

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... Access: Read/write Function: This 8-bit MMR is the SPI baud rate selection register. SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Rev Page ADuC7122 ...

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... ADuC7122 Bit Name Description 8 SPIROW SPIRX overflow overwrite enable. Set by the user, the valid data in the Rx register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. 7 SPIZEN SPI transmit zeros when the Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. ...

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... Figure 35. PLA Element In total, 32 GPIO pins are available on each ADuC7122 for the PLA. These include 16 input pins and 16 output pins that need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins ...

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... ADuC7122 Table 115. PLAELMx MMR Bit Descriptions Bit Value Description 31:11 Reserved. 10:9 Mux 0 control (see Table 118). 8:7 Mux 1 control (see Table 118). 6 Mux 2 control. 1 Set by user to select the output of Mux 0. 0 Cleared by user to select the bit value from the PLADIN register. 5 Mux 3 control. ...

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... PLACLK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modification of any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Access R/W Rev Page ADuC7122 Default Value Access 0x00000000 R/W Default Value Access ...

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... ADuC7122 INTERRUPT SYSTEM There are 27 interrupt sources on the ADuC7122 that are con- trolled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core only recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ) ...

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... FIQSIG is set; otherwise cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. FIQSIG Register Name: FIQSIG Address: 0xFFFF0104 Default Value: 0x00000000 Access: Read only Rev Page ADuC7122 ...

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... UNUSED Figure 36. Interrupt Structure Vectored Interrupt Controller (VIC) The ADuC7122 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. ...

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... A priority level can be set for Timer1. Reserved Reserved bit. T0PI A priority level can be set for Timer0. Reserved Reserved bit. SWINTP A priority level can be set for the software interrupt source. Reserved Interrupt 0 cannot be prioritized. IRQP1 0xFFFF0024 0x00000000 Read and write ADuC7122 ...

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... ADuC7122 Table 133. IRQP1 MMR Bit Designations Bit Name Description 31 Reserved Reserved bit. 30:28 I2C0MPI A priority level can be set for the I2C0 master. 27 Reserved Reserved bit. 26:24 SPIPI A priority level can be set for the SPI. 23 Reserved Reserved bit. 22:20 UARTPI A priority level can be set for the UART ...

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... Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. External Interrupts (IRQ0 to IRQ5) The ADuC7122 provides up to six external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, the appropriate bit must first be set in the FIQEN or IRQEN register ...

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... ADuC7122 Table 140. IRQCONE MMR Bit Designations Bit Value Name 31:12 Reserved 11:10 11 IRQ5SRC[1: 9:8 11 IRQ4SRC[1: 7:6 11 IRQ3SRC[1: 5:4 11 IRQ2SRC[1: 3:2 11 IRQ1SRC[1: 1:0 11 IRQ0SRC[1: Description These bits are reserved and should not be written to. External IRQ5 triggers on falling edge. ...

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... A 1 must be written to this bit in the IRQO interrupt service routine to clear an edge triggered IRQ0 interrupt. 18:0 Reserved These bits are reserved and should not be written to. TIMERS The ADuC7122 has five general-purpose timers/counters.  Timer0  Timer1  Timer2 or wake-up timer  Timer3 or watchdog timer  ...

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... ADuC7122 The Timer0 interface consists of six MMRs, shown in Table 143. Table 143. Timer0 Interface MMRs Name Description T0LD 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. T0CAP 16-bit register that holds the 16-bit value captured by an enabled IRQ event ...

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... This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Table 155. Timer1 Control Register. Name Address T1CON 0xFFFF0328 This 32-bit MMR configures the mode of operation of Timer1. Rev Page ADuC7122 Default Value Access 0x00000 R/W Default Value Access 0x00 W ...

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... ADuC7122 Table 156. T1CON MMR Bit Designations Bit Value Description 31:24 8-bit postscaler. 23 Enable write to postscaler. 22:20 Reserved. 19 Postscaler compare flag interrupt generation selection flag. 17 Event select bit. 1 Set by the user to enable time capture of an event. 0 Cleared by the user to disable time capture of an event. ...

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... T2VAL is a 32-bit register that holds the current value of Timer2. Table 161. Timer2 Control Register Name Address T2CON 0xFFFF0348 This 32-bit MMR configures the mode of operation for Timer2. Rev Page ADuC7122 Default Value Access 0x00000 R/W Default Value Access 0x00 W ...

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... ADuC7122 Table 162. T2CON MMR Bit Designations Bit Value Description 31:11 Reserved. 10:9 Clock source select. 00 Internal 32.768 kHz oscillator (default). 01 Core clock. 10 External 32.768 kHz watch crystal. 11 UCLK. 8 Count up. 1 Set by the user for Timer2 to count up. 0 Cleared by the user for Timer2 to count down (default). ...

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... Timer3 in watchdog mode to prevent a watchdog timer reset event. Table 167. Timer3 Control Register Name T3CON The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 168. Rev Page ADuC7122 Address Default Value Access 0xFFFF0360 0x03D7 R/W Address ...

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... ADuC7122 Table 168. T3CON MMR Bit Designations Bit Value Description 16:9 These bits are reserved and should be written user code. 8 Count up/down enable. 1 Set by user code to configure Timer3 to count up. 0 Cleared by user code to configure Timer3 to count down. 7 Timer3 enable. 1 Set by user code to enable Timer3. ...

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... Timer1 interrupt. T4CON is the configuration MMR. Address Default Value 0xFFFF0380 0x00000 Address Default Value 0xFFFF038C 0x00 Address Default Value 0xFFFF0384 0x0000 Address Default Value 0xFFFF0390 0x00 Address Default Value 0xFFFF0388 0x0000 ADuC7122 Access R/W Access W Access R Access R Access R/W ...

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... ADuC7122 Table 174. T4CON MMR Bit Designations Bit Value Description 31:18 Reserved. Set by user Event select bit. 1 Set by the user to enable time capture of an event. 0 Cleared by the user to disable time capture of an event. 16:12 Event select range 31. The events are as described in the Timers section. ...

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... Chip Scale Package Ball Grid Array [CSP_BGA] 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel Rev Page BALL CORNER BOTTOM VIEW * 1.11 MAX COPLANARITY 0.08 SEATING PLANE Package Option BC-108-4 BC-108-4 ADuC7122 ...

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... ADuC7122 NOTES Rev Page ...

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... NOTES Rev Page ADuC7122 ...

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... ADuC7122 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08755-0-4/10(0) Rev Page ...

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