ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 79

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

VIC MMRs
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
Address:
Default Value:
Access:
Table 130. IRQBASE MMR Bit Designations
Bit
31:16
15:0
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Name:
Address:
Default Value:
Access:
Table 131. IRQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
Read only
R/W
Read only
Reserved
Type
Type
Read only
R/W
IRQBASE
0xFFFF0014
0x00000000
Read and write
IRQVEC
0xFFFF001C
0x00000000
Read only
Initial
Value
0
0
0
0
Initial Value
Reserved
0
Always read as 0.
Description
IRQBASE register value.
Highest priority IRQ source. This is a
value between 0 to 27 representing
the possible interrupt sources. For
example, if the highest currently
active IRQ is Timer1, then these
bits are 00011.
Reserved bits.
Description
Always read as 0
Vector base address
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Priority Registers
IRQP0 Register
Name:
Address:
Default Value:
Access:
Table 132. IRQP0 MMR Bit Designations
Bit
31:27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7
6:4
3:0
IRQP1 Register
Name:
Address:
Default Value:
Access:
Name
Reserved
T4PI
Reserved
T3PI
Reserved
T2PI
Reserved
T1PI
Reserved
T0PI
Reserved
SWINTP
Reserved
IRQP0
0xFFFF0020
0x00000000
Read and write
IRQP1
0xFFFF0024
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for
Timer4.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer3.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer2.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer1.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer0.
Reserved bit.
A priority level of 0 to 7 can be set for the
software interrupt source.
Interrupt 0 cannot be prioritized.
ADuC7122