ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 33

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADC10
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described for the three different modes of
operation: differential mode, pseudo differential mode, and
single-ended mode.
Differential Mode
The ADuC7122 contains a successive approximation ADC
based on two capacitive DACs. Figure 18 and Figure 19 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises control logic, a SAR, and
two capacitive DACs. In Figure 18 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor
arrays acquire the differential signal on the input.
When the ADC starts a conversion (see Figure 19), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator back
into a balanced condition. When the comparator is rebalanced,
the conversion is complete. The control logic generates the ADC
output code. The output impedances of the sources driving the
V
have different settling times, resulting in errors. The input
channel configuration for differential mode is set using the
ADCCP and ADCCN registers.
ADC10
ADC0
ADC0
IN+
and V
MUX
MUX
IN−
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
inputs must be matched; otherwise, the two inputs
Figure 18. ADC Acquisition Phase
Figure 19. ADC Conversion Phase
B
A
A
B
B
A
A
B
V
V
REF
REF
SW1
SW2
SW1
SW2
C
C
C
C
S
S
S
S
SW3
SW3
COMPARATOR
COMPARATOR
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
DAC
DAC
LOGIC
DAC
LOGIC
DAC
Rev. 0 | Page 33 of 96
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the V
of the ADuC7122, and SW2 switches between A (Channel−)
and B (V
low voltage. The input signal on V
V
does not exceed AV
or PADCxN should be enabled for the V
register is used to set Channel− to AINCM or PADCxN, and
the Channel+ can be selected using the ADCCP register.
PADCxP
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The V
on V
channels and two programmable gain ADC channels, which are
enabled using the ADCCP register.
ADC10
Analog Input Structure
Figure 22 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provide ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. Voltage in excess of 300 mV can cause these diodes to
become forward biased and start conducting into the substrate.
These diodes can conduct up to 10 mA without causing irreversi-
ble damage to the part.
The C1 capacitors in Figure 22 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of 16 pF
typical.
ADC0
REF
ADC0
ADC9
V
IN–
+ V
IN+
MUX
is 0 V to V
MUX
IN−
REF
. Note that V
). The V
CHANNEL+
CHANNEL+
CHANNEL–
Figure 20. ADC in Pseudo Differential Mode
IN−
Figure 21. ADC in Single-Ended Mode
input can be floating. The input signal range
CHANNEL–
REF
DD
IN−
. In pseudo differential mode, only AINCM
. The ADuC7122 has 11 fixed gain ADC
B
A
B
A
A
B
input must be connected to ground or a
V
SW1
IN−
REF
SW1
SW2
must be selected so that V
C
C
C
C
S
S
S
S
IN+
SW3
can then vary from V
SW3
IN−
COMPARATOR
COMPARATOR
channel. The ADCCN
ADuC7122
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
REF
CONTROL
CONTROL
IN−
DAC
LOGIC
DAC
DAC
LOGIC
DAC
+ V
input
IN−
IN−
to