ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 59

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

I
The ADuC7122 incorporates two I
separately configured as a fully I
device or as a fully I
both peripherals are identical, only one is explained here.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ e d format that allows arbitration in a multimas-
ter system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The I
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges the last byte, the data transfer is
initiated. This continues until the master issues a stop
condition, and the bus becomes idle.
The I
at any given time. The same I
support master and slave modes.
The I
features:








2
C
Support for repeated start conditions. In master mode, the
ADuC7122 can be programmed to generate a repeated
start. In slave mode, the ADuC7122 recognizes repeated
start conditions.
In master and slave mode, the part recognizes both 7-bit
and 10-bit bus addresses.
In I
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC7122 can be programmed to
return a NACK (no acknowledge). This allows the
validiation of checksum bytes at the end of I
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
2
2
2
2
C peripheral can only be configured as a master or slave
C bus peripheral address in the I
C interface on the ADuC7122 includes the following
C hardware testing. In loopback mode.
2
C master mode, the ADuC7122 supports continuous
2
C bus-compatible slave device. Because
2
2
C system consists of a master
C channel cannot simultaneously
2
C-compatible I
2
C peripherals that can be
2
C bus system is pro-
2
C bus master
2
C transfers.
Rev. 0 | Page 59 of 96
Configuring External Pins for I
The I
I2C0, and P1.0 and P1.1 for I2C1.
P0.0 and P1.0 are the I
the I
(SCL1, SDA1), Bit 0 and Bit 4 of the GP0CON register must be
set to 1 to enable I
pins (SCL2, SDA2), Bit 1 and Bit 5 of the GP1CON register
must be set to 1 to enable I
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CxDIV MMR as follows:
where:
f
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation,
and for 400 kHz,
The I2CxDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2xCID3
registers contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
Master. To be correctly addressed, the seven MSBs of either ID
register must be identical to that of the seven MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC7122 also supports 10-bit addressing mode. When
Bit 1 of I2CxSCTL (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in the I2CxID0
and I2CxID1 registers. The 10-bit address is derived as follows:
I2CxID0[0] is the read/write bit and is not part of the I
address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
UCLK
2
C BUS ADDRESSES
2
DIVH = DIVL = 0xCF
DIVH = 0x28, DIVL = 0x3C
is the clock before the clock divider.
C data signals. For instance, to configure the I2C0 pins
2
2
f
C pins of the ADuC7122 device are P0.0 and P0.1 for
C master in the system generates the serial clock for a
SERIAL
CLOCK

2
C mode. Alternatively, to configure the I2C1
2 (

2
C clock signals, and P0.1 and P1.1 are
DIVH
2
C mode.
f
UCLK
)

(2
2
C Functionality

DIVL
)
ADuC7122
2
C