ADUC7021 Analog Devices, ADUC7021 Datasheet

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ADUC7021

Manufacturer Part Number
ADUC7021
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7021

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
13
Adc # Channels
8
FEATURES
Analog I/O
Microcontroller
Clocking options
Memory
1
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Depending on part model. See Ordering Guide for more information.
Multichannel, 12-bit, 1 MSPS ADC
Fully differential and single-ended modes
0 V to V
12-bit voltage output DACs
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Up to 16 ADC channels
Up to 4 DAC outputs available
REF
analog input range
CMP
XCLKO
ADC11
XCLKI
ADC0
CMP0
CMP1
V
RST
OUT
REF
1
AND PLL
1
OSC
PSM
POR
MUX
12-BIT ADC
BAND GAP
PURPOSE TIMERS
SENSOR
FUNCTIONAL BLOCK DIAGRAM
1MSPS
TEMP
PLA
REF
Precision Analog Microcontroller, 12-Bit
4 GENERAL-
ADuC7019/20/21/22/24/25/26/27/28/29
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
31k × 16 FLASH/EEPROM
2k × 32 SRAM
UART, SPI, I
Figure 1.
ADuC7026
SERIAL I/O
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
On-chip peripherals
Power
Packages and temperature range
Tools
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
2
C
UART, 2× I
Up to 40-pin GPIO port
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator
Programmable logic array (PLA)
External memory interface, up to 512 kB
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP
Fully specified for –40°C to +125°C operation
Low cost QuickStart™ development system
Full third-party support
Analog I/O, ARM7TDMI MCU
JTAG
GPIO
2
C® and SPI serial I/O
12-BIT
12-BIT
12-BIT
12-BIT
DAC
DAC
DAC
DAC
©2005-2011 Analog Devices, Inc. All rights reserved.
EXT. MEMORY
INTERFACE
3-PHASE
PWM
1
DAC0
DAC1
DAC2
DAC3
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
1
H
L
H
L
H
L
1
www.analog.com
1

Related parts for ADUC7021

ADUC7021 Summary of contents

Page 1

... Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...

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... Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Detailed Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 16 ESD Caution................................................................................ 16 Pin Configurations and Function Descriptions ......................... 17 ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17 ADuC7024/ADuC7025 ............................................................. 21 ADuC7026/ADuC7027 ............................................................. 24 ADuC7028................................................................................... 27 ADuC7029................................................................................... 29 Typical Performance Characteristics ........................................... 31 Terminology .................................................................................... 34 ADC Specifications .................................................................... 34 DAC Specifications..................................................................... 34 Overview of the ARM7TDMI Core............................................. 35 Thumb Mode (T) ...

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REVISION HISTORY 5/11—Rev Rev. D Changes to Table 4 ..........................................................................11 Changes to Table 105 ......................................................................67 Updated Outline Dimensions........................................................91 Changes to Ordering Guide...........................................................95 12/09—Rev Rev. C Added ADuC7029 Part ..................................................... Universal Added Table Numbers and Renumbered Tables............... ...

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ADuC7019/20/21/22/24/25/26/27/28/29 GENERAL DESCRIPTION The ADuC7019/20/21/22/24/25/26/27/28/29 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash®/EE memory on a single chip. The ADC consists single-ended inputs. An additional four ...

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DETAILED BLOCK DIAGRAM ADC0 77 ADC1 78 ADC2/CMP0 79 ADC3/CMP1 80 ADC4 1 ADC5 2 ADC6 3 MUX ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADC11 76 SENSOR ADCNEG 9 MUX DAC BM/P0.0/CMP /PLAI[7]/MS0 20 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 SPECIFICATIONS AV = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity 3, 4 Differential ...

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Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance 4, 6 Hysteresis Response Time TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy POWER SUPPLY MONITOR ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Parameter MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element ...

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TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min CLK MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t HOLD_ADDR_BEFORE_WR_L t WR_L_AFTER_AE_L t 8 DATA_AFTER_WR_L WR_H_AFTER_CLKH t HOLD_DATA_AFTER_WR_H t BEN_AFTER_AE_L ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 3. External Memory Read Cycle Parameter Min 1 CLK 1/MD clock t 4 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t RD_L_AFTER_AE_L t 0 RD_H_AFTER_CLKH DATA_BEFORE_RD_H t 8 DATA_AFTER_RD_H t RELEASE_MS_AFTER_RD_H ...

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Table Timing in Fast Mode (400 kHz) Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 6. SPI Master Mode Timing (Phase Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK ...

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Table 7. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge DOSU ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 8. SPI Slave Mode Timing (Phsae Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV ...

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Table 9. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t ...

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ADuC7019/20/21/22/24/25/26/27/28/29 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GND otherwise noted. Table 10. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage to IOGND Digital Output Voltage ...

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... INDICATOR ADC6 3 ADC7 4 GND 5 REF ADuC7021 DAC0/ADC12 6 TOP VIEW DAC1/ADC13 7 (Not to Scale) TMS 8 TDI 9 /PLAI[7] 10 OUT Figure 11. 40-Lead LFCSP_VQ Pin Configuration (ADuC7021) Rev Page P1.3/SPM3/PLAI[3] 29 P1.4/SPM4/PLAI[4]/IRQ2 28 P1.5/SPM5/PLAI[5]/IRQ3 27 P1.6/SPM6/PLAI[6] 26 P1.7/SPM7/PLAO[0] 25 XCLKI 24 XCLKO 23 P0.7/ECLK/XCLK/SPM8/PLAO[4] 22 P2.0/SPM9/PLAO[5]/CONV START 21 IRQ1/P0.5/ADC ...

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... ADuC7019/20/21/22/24/25/26/27/28/29 BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) Pin No. 7019/7020 7021 7022 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ‒ ADC5 ‒ ADC6 ‒ ADC7 ‒ ‒ ...

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Pin No. 7019/7020 7021 7022 Mnemonic BM/P0.0/CMP P0.6/T1/MRST/PLAO[ TCK TDO IOGND IOV DGND ...

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... V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. Exposed Paddle. The pin configuration for the ADuC7019/ADuC7020/ ADuC7021/ADuC7022 has an exposed paddle that must be left unconnected. Rev Page ...

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ADuC7024/ADuC7025 BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. Figure 13. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025) P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] ADuC7019/20/21/22/24/25/26/27/28/29 ADC4 1 PIN 1 ADC5 2 ADC6 3 INDICATOR ADC7 4 ADC8 5 ADuC7024/ ADC9 6 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 GND REF 8 ADCNEG 9 DAC0/ADC12 10 DAC1/ADC13 11 TMS 12 TDI ...

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Pin No. Mnemonic 37 P3.6/PWM /PLAI[14] TRIP 38 P3.7/PWM /PLAI[15] SYNC 39 P1.7/SPM7/PLAO[0] 40 P1.6/SPM6/PLAI[6] 41 IOGND 42 IOV DD 43 P4.0/PLAO[8] 44 P4.1/PLAO[9] 45 P1.5/SPM5/PLAI[5]/IRQ3 46 P1.4/SPM4/PLAI[4]/IRQ2 47 P1.3/SPM3/PLAI[3] 48 P1.2/SPM2/PLAI[2] 49 P1.1/SPM1/PLAI[1] 50 P1.0/T1/SPM0/PLAI[0] 51 P4.2/PLAO[10] 52 P4.3/PLAO[11] ...

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ADuC7019/20/21/22/24/25/26/27/28/29 ADuC7026/ADuC7027 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GND REF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2 /BLE H P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMP /PLAI[7]/MS0 OUT Table 13. Pin Function Descriptions (ADuC7026/ADuC7027) Pin No. Mnemonic 1 ADC4 2 ADC5 ...

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Pin No. Mnemonic 15 TDI 16 P0.1/PWM2 /BLE H 17 P2.3/AE 18 P4.6/AD14/PLAO[14] 19 P4.7/AD15/PLAO[15] 20 BM/P0.0/CMP /PLAI[7]/MS0 OUT 21 P0.6/T1/MRST/PLAO[3] 22 TCK 23 TDO 24 P0.2/PWM2 /BHE L 25 IOGND 26 IOV DGND 29 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Pin No. Mnemonic 46 P3.6/AD6/PWM /PLAI[14] TRIP 47 P3.7/AD7/PWM /PLAI[15] SYNC 48 P2.7/PWM1 /MS3 L 49 P2.1/WS/PWM0 /PLAO[ P2.2/RS/PWM0 /PLAO[ P1.7/SPM7/PLAO[0] 52 P1.6/SPM6/PLAI[6] 53 IOGND 54 IOV DD 55 P4.0/AD8/PLAO[8] 56 P4.1/AD9/PLAO[9] 57 P1.5/SPM5/PLAI[5]/IRQ3 58 ...

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ADUC7028 Table 14. Pin Function Descriptions (ADuC7028) Ball No. Mnemonic A1 ADC3/CMP1 A2 DACV AGND A5 DACGND A6 P4.2/PLAO[10] A7 P1.1/SPM1/PLAI[1] A8 P1.2/SPM2/PLAI[2] B1 ADC4 B2 ADC2/CMP0 B3 ADC1 B4 DAC REF B5 V REF ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Ball No. Mnemonic D7 P1.6/SPM6/PLAI[6] D8 IOV DD E1 DAC3 E2 DAC2 E3 DAC1 E4 P3.0/PWM0 /PLAI[ P3.2/PWM1 /PLAI[10 P1.5/SPM5/PLAI[5]/IRQ3 E7 P3.7/PWM /PLAI[15] SYNC E8 XCLKI F1 P4.6/PLAO[14] F2 TDI F3 DAC0s F4 P3.1/PWM0 /PLAI[9] ...

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ADUC7029 Table 15. Pin Function Descriptions (ADuC7029) Ball No. Mnemonic A1 ADC3/CMP1 A2 ADC1 A3 ADC0 REF A6 P1.0/T1/SPM0/PLAI[0] A7 P1.1/SPM1/PLAI[1] B1 ADC6 B2 ADC5 B3 ADC4 B4 AGND B5 DAC REF B6 P1.4/SPM4/PLAI[4]/IRQ2 B7 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Ball No. Mnemonic E1 TMS E2 BM/P0.0/CMP /PLAI[7] OUT E3 DAC2 E4 IOV DD E5 P3.2/PWM1 /PLAI[10 P3.5/PWM2 /PLAI[13 P0.7/ECLK/XCLK/SPM8/PLAO[4] F1 TDI F2 P0.6/T1/MRST/PLAO[3] F3 IOGND F4 P3.1/PWM0 /PLAI[ P3.0/PWM0 /PLAI[ ...

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TYPICAL PERFORMANCE CHARACTERISTICS 1 774kSPS S 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES Figure 18. Typical INL Error 1 1MSPS S 0.8 0.6 0.4 0.2 0 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1161 1162 BIN Figure 24. Code Histogram Plot 774 kSPS –20 –40 –60 –80 –100 –120 –140 –160 0 100 FREQUENCY (kHz) Figure 25. Dynamic ...

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TEMPERATURE (°C) Figure 30. Current Consumption vs. Temperature @ 7.85 7.80 7.75 7.70 7.65 7.60 7.55 7.50 7.45 7.40 – ...

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ADuC7019/20/21/22/24/25/26/27/28/29 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below ...

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OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits bits. ...

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ADuC7019/20/21/22/24/25/26/27/28/29 • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: • The longest time the request can take to pass through the ...

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MEMORY ORGANIZATION The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two separate blocks of memory SRAM and on-chip Flash/EE memory. The on-chip Flash/EE memory is available to the user, and the remaining 2 kB are reserved ...

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ADuC7019/20/21/22/24/25/26/27/28/29 0xFFFFFFFF 0xFFFFFC3C PWM 0xFFFFFC00 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 I2C1 0xFFFF0900 0xFFFF0848 I2C0 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND GAP REFERENCE 0xFFFF048C 0xFFFF0448 ...

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Access Address Name Byte Type Reference Address Base = 0xFFFF0480 0x048C REFCON 1 R/W ADC Address Base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0504 ADCCP 1 R/W 0x0508 ADCCN 1 R/W 0x050C ADCSTA 1 R 0x0510 ADCDAT 4 R 0x0514 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Access Address Name Byte Type PLA Base Address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0B04 PLAELM1 2 R/W 0x0B08 PLAELM2 2 R/W 0x0B0C PLAELM3 2 R/W 0x0B10 PLAELM4 2 R/W 0x0B14 PLAELM5 2 R/W 0x0B18 PLAELM6 2 R/W 0x0B1C ...

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ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source is ...

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ADuC7019/20/21/22/24/25/26/27/28/29 TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits. The 12-bit result ...

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Table 18. ADCCON MMR Bit Designations Bit Value Description 15:13 Reserved. 12:10 ADC clock speed. 000 fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. 001 fADC/2 (default value). 010 fADC/4. 011 fADC/8. ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 22. ADCCN MMR Bit Designation Bit Value Description 7:5 Reserved. 4:0 Negative channel selection bits. 00000 ADC0. 00001 ADC1. 00010 ADC2. 00011 ADC3. 00100 ADC4. 00101 ADC5. 00110 ADC6. 00111 ADC7. 01000 ADC8. 01001 ADC9. 01010 ADC10. 01011 ...

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Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7019/20/21/22/24/25/26/27/28/29. SW2 switches between A (Channel−) and The V REF connected to ground or a low voltage. The input signal on V ...

Page 46

ADuC7019/20/21/22/24/25/26/27/28/29 Table 28. V Ranges Min V Max DD REF CM CM 3.3 V 2.5 V 1.25 V 2.05 V 2.048 V 1.024 V 2.276 V 1.25 V 0.75 V 2.55 V 3.0 V 2.5 V ...

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NONVOLATILE FLASH/EE MEMORY The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase ...

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ADuC7019/20/21/22/24/25/26/27/28/29 SECURITY The Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 42) protects the 62 kB from being read through JTAG programming mode. The other ...

Page 49

Table 35. FEECON Register Name Address Default Value FEECON 0xFFFFF808 0x07 FEECON is an 8-bit command register. The commands are described in Table 36. Table 36. Command Codes in FEECON Code Command Description 1 0x00 Null Idle state. 1 0x01 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 EXECUTION TIME FROM SRAM AND FLASH/EE Execution from SRAM Fetching instructions from SRAM takes one clock cycle; the access time of the SRAM is 2 ns, and a clock cycle minimum. However, if the instruction involves ...

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Reset Operation There are four kinds of reset: external, power-on, watchdog expiration, and software force. The RSTSTA register indicates the source of the last reset, and RSTCLR allows clearing of the RSTSTA register. These registers can be used during a ...

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ADuC7019/20/21/22/24/25/26/27/28/29 OTHER ANALOG PERIPHERALS DAC The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two, three, or four 12-bit voltage output DACs on-chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ...

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Linearity degradation near ground and AV ration of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 54. The dotted line in Figure 54 indicates the ideal transfer function, and ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Input offset voltage ( the difference between the center of OS the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (V width of the hysteresis range. Comparator Interface The ...

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Example source code T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON ...

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ADuC7019/20/21/22/24/25/26/27/28/29 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs: PLLCON (see Table 61) and POWCON (see Table 64). PLLCON controls the operating mode of the clock system, whereas POWCON controls the ...

Page 57

DIGITAL PERIPHERALS 3-PHASE PWM Each ADuC7019/20/21/22/24/25/26/27/28/29 provides a flexible and programmable, 3-phase pulse-width modulation (PWM) waveform generator. It can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction motor control (ACIM). ...

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ADuC7019/20/21/22/24/25/26/27/28/29 DESCRIPTION OF THE PWM BLOCK A functional block diagram of the PWM controller is shown in Figure 58. The generation of the six output PWM signals on Pin PWM0 to Pin PWM2 is controlled by the following four H ...

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The PWMDAT1 register is a 10-bit register with a maximum value of 0x3FF (= 1023), which corresponds to a maximum programmed dead time 1023 × 2 × 1023 × 2 × 24 ×10 D(max) CORE ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Both switching edges are moved by an equal amount (PWMDAT1 × preserve the symmetrical output CORE patterns. Also shown are the PWMSYNC pulse and Bit 0 of the PWMSTA register, which indicates whether operation is in ...

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Output Control Unit The operation of the output control unit is controlled by the 9-bit read/write PWMEN register. This register controls two distinct features of the output control unit that are directly useful in the control of electronic counter measures ...

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ADuC7019/20/21/22/24/25/26/27/28/29 The GDCLK value can range from 0 to 255, corresponding to a programmable chopping frequency rate of 40.8 kHz to 10.44 MHz for a 41.78 MHz core frequency. The gate drive features must be programmed before operation of the ...

Page 63

Table 70. PWMCFG Register Name Address Default Value PWMCFG 0xFFFFFC10 0x0000 PWMCFG is a gate chopping register. Table 71. PWMCFG MMR Bit Descriptions Bit Name Description 15:10 Reserved. 9 CHOPLO Low-side gate chopping enable bit. 8 CHOPHI High-side gate chopping ...

Page 64

ADuC7019/20/21/22/24/25/26/27/28/29 Table 78. GPIO Pin Function Descriptions Configuration Port Pin P0.0 GPIO CMP P0.1 GPIO PWM2 H P0.2 GPIO PWM2 L P0.3 GPIO TRST P0.4 GPIO/IRQ0 PWM TRIP P0.5 GPIO/IRQ1 ADC BUSY P0.6 GPIO/T1 MRST P0.7 GPIO ...

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Table 83. GPxDAT Registers Name Address Default Value GP0DAT 0xFFFFF420 0x000000XX GP1DAT 0xFFFFF430 0x000000XX GP2DAT 0xFFFFF440 0x000000XX GP3DAT 0xFFFFF450 0x000000XX GP4DAT 0xFFFFF460 0x000000XX GPxDAT are Port x configuration and data registers. They ...

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ADuC7019/20/21/22/24/25/26/27/28/29 The serial communication adopts an asynchronous protocol, which supports various word lengths, stop bits, and parity generation options selectable in the configuration register. Baud Rate Generation There are two ways of generating the UART baud rate, normal 450 UART ...

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Table 98. COMIID0 Register Name Address Default Value COMIID0 0xFFFF0708 0x01 COMIID0 is the interrupt identification register. Table 99. COMIID0 MMR Bit Descriptions Bit 2:1 Bit 0 Status Bits NINT Priority Definition 00 1 N/A No interrupt ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 107. COMSTA1 MMR Bit Descriptions Bit Name Description 7 DCD Data carrier detect Ring indicator. 5 DSR Data set ready. 4 CTS Clear to send. 3 DDCD Delta DCD. Set automatically if DCD changed state since ...

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Table 114. COMIID1 MMR Bit Descriptions Bit 3:1 Status Bit 0 Bits NINT Priority Definition 000 1 No interrupt 110 0 2 Matching network address 101 0 3 Address transmitted, buffer empty 011 0 1 Receive line status interrupt 010 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 SPI Registers The following MMR registers are used to control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. Table 117. SPISTA Register Name Address Default Value SPISTA 0xFFFF0A00 0x00 SPISTA is an 8-bit read-only status register. Only Bit ...

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I C-COMPATIBLE INTERFACES The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed interfaces. The I C interfaces are both implemented as a hard- ware master and a full slave interface. Because the two I faces are identical, this data ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 127. I2C0SSTA MMR Bit Descriptions Bit Value Description 31:15 Reserved. These bits should be written Start decode bit. Set by hardware if the device receives a valid start plus matching address. Cleared ...

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Table 135. I2CxALT Registers Name Address Default Value I2C0ALT 0xFFFF0828 0x00 I2C1ALT 0xFFFF0928 0x00 I2CxALT are hardware general call ID registers used in slave mode. Table 137. I2C0CFG MMR Bit Descriptions Bit Description 31:5 Reserved. These bits should be written ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 138. I2CxDIV Registers Name Address Default Value I2C0DIV 0xFFFF0830 0x1F1F I2C1DIV 0xFFFF0930 0x1F1F I2CxDIV are the clock divider registers. Table 139. I2CxIDx Registers Name Address Default Value I2C0ID0 0xFFFF0838 0x00 I2C0ID1 0xFFFF083C 0x00 I2C0ID2 0xFFFF0840 0x00 I2C0ID3 0xFFFF0844 ...

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PROGRAMMABLE LOGIC ARRAY (PLA) Every ADuC7019/20/21/22/24/25/26/27/28/29 integrates a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 146. PLACLK Register Name Address Default Value PLACLK 0xFFFF0B40 0x00 PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input ...

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Table 151. PLAADC Register Name Address Default Value PLAADC 0xFFFF0B48 0x00000000 PLAADC is the PLA source for the ADC start conversion signal. Table 152. PLAADC MMR Bit Descriptions Bit Value Description 31:5 Reserved. 4 ADC start conversion enable bit. Set ...

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ADuC7019/20/21/22/24/25/26/27/28/29 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 23 interrupt sources on the ADuC7019/20/21/22/ 24/25/26/27/28/29 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Four additional interrupt sources are ...

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FIQ The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ ...

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ADuC7019/20/21/22/24/25/26/27/28/29 When using an asynchronous clock-to-clock timer, the interrupt in the timer block may take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared ...

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Table 177. T1CON MMR Bit Descriptions Bit Value Description 31:18 Reserved. 17 Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 Event select range, 0 ...

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ADuC7019/20/21/22/24/25/26/27/28/29 Table 183. T2CON MMR Bit Descriptions Bit Value Description 31:11 Reserved. 10:9 Clock source. 00 External crystal. 01 External crystal. 10 Internal oscillator Core clock (41 MHz/2 8 Count up. Set by user for Timer2 to count ...

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Table 188. T3CON MMR Bit Descriptions Bit Value Description 31:9 Reserved. 8 Count up. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down by default. 7 Timer3 enable bit. Set by user to ...

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ADuC7019/20/21/22/24/25/26/27/28/29 ADuC7026/ ADuC7027 A16 AD15:AD0 LATCH AE MS0 MS1 WS RS Figure 70. Interfacing to External EEPROM/RAM Table 192. XMCFG Register Name Address Default Value XMCFG 0xFFFFF000 0x00 XMCFG is set enable external memory access. This must ...

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UCLK AD[16:0] ADDRESS MSx AE RS Figure 71. External Memory Read Cycle UCLK AD[16:0] ADDRESS EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) MSx AE RS Figure 72. External Memory Read Cycle with Address Hold and Bus Turn Cycles Rev. D ...

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ADuC7019/20/21/22/24/25/26/27/28/29 UCLK AD[16:0] MSx AE WS Figure 73. External Memory Write Cycle with Address and Write Hold Cycles UCLK AD[16:0] MSx AE WS ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) ADDRESS 1 ...

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HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7019/20/21/22/24/25/26/27/28/29 operational power supply voltage range is 2 3.6 V. Separate analog and digital power supply pins (AV and IOV kept relatively free of noisy digital signals often ...

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ADuC7019/20/21/22/24/25/26/27/28/29 GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7019/20/21/22/24/25/26/27/28/29-based designs to achieve optimum performance from the ADCs and DAC. Although the parts ...

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POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7019/20/21/22/24/25/26/27/28/29. For LV typical, the internal POR holds the part in reset above 2. internal timer times out for, typically, 128 ms before the ...

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ADuC7019/20/21/22/24/25/26/27/28/29 DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7019/20/21/22/24/25/26/27/28/29 family. • The ADuC7026 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. Because the ADuC7026 contains the ...

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OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ADuC7019/20/21/22/24/25/26/27/28/29 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP ...

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ADuC7019/20/21/22/24/25/26/27/28/29 BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW 9.00 0.60 MAX 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.50 0. 0.30 ...

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SEATING 0.05 0.08 PLANE COPLANARITY VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BDD Figure 88. 80-Lead Low Profile Quad Flat Package [LQFP] Dimensions shown in millimeters ...

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ADuC7019/20/21/22/24/25/26/27/28/29 1.20 MAX 5.05 5. BALL A1 INDICATOR 3.90 TOP VIEW BSC SQ BOTTOM 0.65 VIEW DETAIL A BSC DETAIL A 0.35 0.20 0.45 0.40 0.35 BALL DIAMETER Figure. 49-Ball Chip Scale Package Ball ...

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... ADuC7020BCPZ62 5 4 ADuC7020BCPZ62-RL7 5 4 ADuC7020BCPZ62I 5 4 ADuC7020BCPZ62I- ADuC7020BCPZ62IRL7 5 4 ADuC7021BCPZ62 8 2 ADuC7021BCPZ62- ADuC7021BCPZ62-RL7 8 2 ADuC7021BCPZ62I 8 2 ADuC7021BCPZ62I- ADuC7021BCPZ32 8 2 ADuC7021BCPZ32-RL7 8 2 ADuC7022BCPZ62 10 ADuC7022BCPZ62-RL7 10 ADuC7022BCPZ32 10 ADuC7022BCPZ32-RL 10 ADuC7024BCPZ62 10 2 ADuC7024BCPZ62-RL7 10 2 ADuC7024BCPZ62I 10 2 ADuC7024BCPZ62I- ADuC7024BSTZ62 10 2 ADuC7024BSTZ62- ADuC7025BCPZ62 ...

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... One of the ADC channels is internally buffered for ADuC7019 models refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). ©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. FLASH/ Down- Temperature ...

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