ADUC7021 Analog Devices, ADUC7021 Datasheet - Page 84

• Manufacturer Part Number: ADUC7021
• Manufacturer: Analog Devices

Specifications of ADUC7021

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 13
• Adc # Channels: 8

ADuC7019/20/21/22/24/25/26/27/28/29
Table 192. XMCFG Register
Name
XMCFG
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
Table 193. XMxCON Registers
Name
XM0CON
XM1CON
XM2CON
XM3CON
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 194. XMxCON MMR Bit Descriptions
Bit
1
0
Description
Selects data bus width. Set by user to select a 16-bit data
bus. Cleared by user to select an 8-bit data bus.
Enables memory region. Set by user to enable the memory
region. Cleared by user to disable the memory region.
ADuC7026/
ADuC7027
AD15:AD0
Figure 70. Interfacing to External EEPROM/RAM
Address
0xFFFFF000
Address
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
MS0
MS1
A16
WS
AE
RS
LATCH
Default Value
0x00
Default Value
0x00
0x00
0x00
0x00
D0:D15
A0:A15
CS
WE
OE
D0:D7
A16
A0:A15
CS
WE
OE
64k × 16-BIT
128k × 8-BIT
EEPROM
RAM
Access
R/W
Access
R/W
R/W
R/W
R/W
Rev. D | Page 84 of 96
Table 195. XMxPAR Registers
Name
XM0PAR
XM1PAR
XM2PAR
XM3PAR
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 196. XMxPAR MMR Bit Descriptions
Bit
15
14:12
11
10
9
8
7:4
3:0
Figure 71, Figure 72, Figure 73, and Figure 74 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
Reserved.
Description
Enable byte write strobe. This bit is used only for two,
8-bit memory devices sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE and BLE signals. Cleared by user to use BHE and BLE
signals.
Number of wait states on the address latch enable STROBE.
Extra address hold time. Set by user to disable extra hold
time. Cleared by user to enable one clock cycle of hold
on the address in read and write.
Extra bus transition time on read. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the read strobe (RS).
Extra bus transition time on write. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the write strobe (WS).
Number of write wait states. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Number of read wait states. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Address
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
Default Value
0x70FF
0x70FF
0x70FF
0x70FF
Access
R/W
R/W
R/W
R/W