ADUC7023 Analog Devices, ADUC7023 Datasheet

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ADUC7023

Manufacturer Part Number
ADUC7023
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7023

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
20
Adc # Channels
12
Other
PWM
FEATURES
Analog I/O
Microcontroller
Clocking options
Memory
Vectored interrupt controller for FIQ and IRQ
On-chip peripherals
Power
Packages and temperature range
Fully specified for −40°C to +125°C operation
Tools
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Multichannel, 12-bit, 1 MSPS ADC
Fully differential and single-ended modes
0 V to V
12-bit voltage output DACs
On-chip voltage reference
On-chip temperature sensor
Voltage comparator
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
2× fully I
SPI (20 Mbps in master mode, 10 Mbps in slave mode)
Up to 20 GPIO pins
3× general-purpose timers
Programmable logic array (PLA)
16-bit, 5-channel PWM
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz
32-lead 5 mm × 5 mm LFCSP
40-lead LFCSP
Low cost QuickStart development system
Full third-party support
With 4-byte FIFO on input and output stages
All GPIOs are 5 V tolerant
Watchdog timer (WDT)
16 PLA elements
Up to 12 ADC channels
4 DAC outputs available
REF
2
C-compatible channels
analog input range
Precision Analog Microcontroller, 12-Bit Analog
I/O, ARM7TDMI MCU with Enhanced IRQ Handler
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
APPLICATIONS
Optical networking
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems
GENERAL DESCRIPTION
The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data
acquisition system, incorporating high performance multichannel
ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional
four inputs are available but are multiplexed with the four DAC
output pins. The ADC can operate in single-ended or differential input
modes. The ADC input voltage is 0 V to V
reference, temperature sensor, and voltage comparator complete the
ADC peripheral set.
The DAC output range is programmable to one of two voltage
ranges. The DAC outputs have an enhanced feature of being able to
retain their output voltage during a watchdog or software reset
sequence.
The devices operate from an on-chip oscillator and a PLL,
generating an internal high frequency clock of 41.78 MHz. This
clock is routed through a programmable clock divider from which
the MCU core clock operating frequency is generated. The
microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC
machine that offers up to 41 MIPS peak performance. Eight
kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE
memory are provided on chip. The ARM7TDMI core views all
memory and registers as a single linear array.
The ADuC7023 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt levels
are supported.
On-chip factory firmware supports in-circuit download via the I
serial interface port, and nonintrusive emulation is supported via
the JTAG interface. These features are incorporated into a low cost
QuickStart™ development system supporting this MicroConverter®
family. The part contains a 16-bit PWM with five output signals.
For communication purposes, the part contains 2 × I
can be individually configured for master or slave mode. An SPI
interface supporting both master and slave modes is also provided.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. The ADuC7023 is
available in either a 32-lead or 40-lead LFCSP package.
©2010 Analog Devices, Inc. All rights reserved.
REF
ADuC7023
. A low drift band gap
2
www.analog.com
C channels that
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Related parts for ADUC7023

ADUC7023 Summary of contents

Page 1

... Smart sensors, precision instrumentation Base station systems GENERAL DESCRIPTION The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data acquisition system, incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins ...

Page 2

... ADuC7023 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 13 ESD Caution ................................................................................ 13 Pin Configurations and Function Descriptions ......................... 14 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 18 ADC Specifications .................................................................... 18 DAC Specifications..................................................................... 18 Overview of the ARM7TDMI Core ............................................. 19 Thumb Mode (T) ........................................................................ 19 Long Multiply (M) ...................................................................... 19 EmbeddedICE (I) ...

Page 3

... Change to FIQSTAN Register Section ......................................... 81 Change to T2CLRI Register Section ............................................. 85 6/10—Rev Rev. A Changes to Temperature Sensor Parameter in Table 1 ................ 6 Changes to Table 24 ........................................................................ 29 Changes to Temperature Sensor Section ..................................... 34 Changes to DACBKEY0 Register Section and to Table 43 ........ 47 Changes to Ordering Guide ........................................................... 93 1/10—Revision 0: Initial Version Rev Page ADuC7023 ...

Page 4

... ADC0 MUX ADC12 ADC2/CMP0 ADC3/CMP1 CMP OUT V REF OSC XCLKI AND PLL XCLKO PSM RST POR ADuC7023 1MSPS 12-BIT ADC 40-LEAD LFCSP TEMP SENSOR VECTORED BAND GAP INTERRUPT REF CONTROLLER ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 2k × 32 SRAM PLA 31k × 16 FLASH/EEPROM ...

Page 5

... Ω Rev Page ADuC7023 = −40°C to +125°C, unless otherwise noted. A Test Conditions/Comments Eight acquisition clocks and f /2 ADC 2.5 V internal reference 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input voltage kHz sine wave, f ...

Page 6

... ADuC7023 Parameter DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage Input Offset Voltage Drift Input offset Current Input Bias Current Gain Unity-Gain Frequency CMRR Settling Time Output Slew Rate PSRR DAC AC CHARACTERISTICS Voltage Output Settling Time ...

Page 7

... Figure 28. Based on external ADC ) as long as this value is within the ADC voltage input range specified REF . REF ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. J Rev Page ADuC7023 Test Conditions/Comments 85° 125°C A Core clock = 41 ...

Page 8

... ADuC7023 TIMING SPECIFICATIONS 2 Table Timing in Fast Mode (400 kHz) Parameter Description t SCLK low pulse width L t SCLK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time DHD t Setup time for repeated start RSU ...

Page 9

... BIT 6 TO BIT 1 t DSU t DHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev Page Min Typ (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 1 × t UCLK 2 × t UCLK LSB LSB IN ADuC7023 Max Unit 12.5 ns 12.5 ns 12.5 ns 12.5 ns ...

Page 10

... ADuC7023 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge DOSU t Data input setup time before SCLK edge ...

Page 11

... MSB IN BIT 6 TO BIT 1 t DSU t DHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev Page Typ Max (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 25 UCLK UCLK 5 12.5 5 12.5 5 12.5 5 12.5 t SFS LSB LSB IN ADuC7023 Unit ...

Page 12

... ADuC7023 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge DSU t Data input hold time after SCLK edge ...

Page 13

... Only one absolute maximum rating can be applied at any one time. −0 IOV + 0 −0 0 −0 0.3 V ESD CAUTION DD −0 0 −40°C to +125°C −65°C to +150°C 150°C 26°C/W 32.5°C/W 240°C 260°C Rev Page ADuC7023 ...

Page 14

... DAC0 Voltage Output or ADC Input. DAC1 Voltage Output or ADC Input. Rev Page P0.3/PLAO[9]/TCK DD GND 2 23 P0.2/PLAO[8]/TDI REF 3 22 DAC0 P0.1/PLAI[9]/TDO ADuC7023 DAC1 4 21 P0.0/nTRST/ADC TOP VIEW DAC2 5 20 TMS (Not to Scale) RTCK DAC3 ...

Page 15

... ADC Busy Signal. Programmable Logic Array Input Element 8. Boot Mode Entry Pin. The ADuC7023 enters I low at reset with a flash address 0x800014 = 0xFFFFFFFFF. The ADuC7023 executes code pulled high at reset low at reset with a flash address 0x800014 not equal to 0xFFFFFFFFF. ...

Page 16

... ADuC7023 Pin No. 40-LFCSP 32-LFCSP Mnemonic 9 7 P0.4/IRQ0/SCL0/PLAI[0]/CONV 10 8 P0.5/SDA0/PLAI[1]/COMP 11 9 P0.6/MISO/SCL1/PLAI[ P0.7/MOSI/SDA1/PLAO[ XCLKI 22 18 XCLKO 16 N/A P1.7/PWM3/SDA1/PLAI[6] 15 N/A P1.6/PWM2/SCL1/PLAI[5] 29 N/A P1.5/ADC6/PWM 7 N/A P1.4/ADC10/PLAO[ P1.3/ADC5/IRQ3/PLAI[ P1.2/ADC4/IRQ2/PLAI[3]/ECLK P1.1/SS/IRQ1/PWM1/PLAO[2]/ P1.0/SPICLK/PWM0/PLAO[ REF 40 32 AGND Description General-Purpose Input and Output Port 0.4/External Interrupt Request ...

Page 17

... Rev Page 500 1000 1500 2000 2500 3000 ADC CODES SAMPLING RATE = 950kSPS WORST CASE POSITIVE = 1.09, CODE = 4032 WORST CASE NEGATIVE = –0.98, CODE = 3422 = 950 kSPS, External 1.0 V Reference Used ADC 0 20,000 40,000 60,000 80,000 FREQUENCY (Hz) ADuC7023 3500 4095 104,400 ...

Page 18

... ADuC7023 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ ...

Page 19

... R11_FIQ R11 R12_FIQ R12 R13_FIQ R13 R14_FIQ R14 R15 (PC) CPSR SPSR_FIQ FIQ USER MODE MODE Figure 14. Register Organization Rev Page ADuC7023 USABLE IN USER MODE SYSTEM MODES ONLY R13_UND R13_IRQ R13_ABT R14_UND R14_IRQ R13_SVC R14_ABT R14_SVC SPSR_UND SPSR_IRQ SPSR_ABT SPSR_SVC SVC ...

Page 20

... ADuC7023 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd. INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: the longest time the request can take ...

Page 21

... Access to the AHB is one cycle, and 0x00000004 access to the APB is two cycles. All peripherals on the ADuC7023 0x00000000 are on the APB except the Flash/EE memory and the GPIOs. Rev Page ...

Page 22

... ADuC7023 0xFFFFFFFF 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0FBF PWM 0xFFFF0F80 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND GAP REFERENCE 0xFFFF048C 0xFFFF0448 POWER SUPPLY MONITOR 0xFFFF0440 ...

Page 23

... RSTCLR MMR for clearing RSTSTA register. 0xXX 0x76 should be written to this register before writing to RSTCFG. 0x00 This register allows the DAC and GPIO outputs to retain state after a watchdog or software reset. 0xXX 0xB1 should be written to this register after writing to RSTCFG. Rev Page ADuC7023 ...

Page 24

... ADuC7023 Table 12. Timer Address Base = 0xFFFF0300 Address Name Byte 0x0300 T0LD 2 0x0304 T0VAL 2 0x0308 T0CON 2 0x030C T0CLRI 1 0x0320 T1LD 4 0x0324 T1VAL 4 0x0328 T1CON 4 0x032C T1CLRI 1 0x0330 T1CAP 4 0x0360 T2LD 2 0x0364 T2VAL 2 0x0368 T2CON 2 0x036C T2CLRI 1 1 N/A means not applicable. Table 13. PLL/PSM Base Address = 0xFFFF0400 ...

Page 25

... Temperature sensor chopping enable register. Temperature sensor reference value. Description DAC0 control MMR. DAC0 data MMR. DAC1 control MMR. DAC1 data MMR. DAC2 control MMR. DAC2 data MMR. DAC3 control MMR. DAC3 data MMR. DAC Configuration MMR DAC Key0 MMR DAC Key1 MMR ADuC7023 ...

Page 26

... ADuC7023 Address Name Byte Access Type 0x0914 I2C1MCNT1 1 R 0x0918 I2C1ADR0 1 R/W 0x091C I2C1ADR1 1 R/W 0x0924 I2C1DIV 2 R/W 0x0928 I2C1SCON 2 R/W 0x092C I2C1SSTA 2 R/W 0x0930 I2C1SRX 1 R 0x0934 I2C1STX 1 W 0x0938 I2C1ALT 1 R/W 0x093C I2C1ID0 1 R/W 0x0940 I2C1ID1 1 R/W 0x0944 I2C1ID2 1 R/W 0x0948 I2C1ID3 1 R/W 0x094C I2C1FSTA 2 R/W Table 19. SPI Base Address = 0xFFFF0A00 ...

Page 27

... R 0xFFFFFF R/W 0x00000000 R/W 0xFFFFFFFF Rev Page ADuC7023 Description GPIO Port0 control MMR. GPIO Port1 control MMR. GPIO Port2 control MMR. GPIO Port0 data control MMR. GPIO Port0 data set MMR. GPIO Port0 data clear MMR. GPIO Port0 pull-up disable MMR. ...

Page 28

... ADuC7023 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, a differential track-and-hold, an on-chip reference, and an ADC. ...

Page 29

... Read/write ADCCON is an ADC control register that allows the programmer to enable the ADC peripheral, select the mode of operation of the ADC (either in single- ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. This MMR is described in Table 24. ADuC7023 ADCSTA = 1 ...

Page 30

... ADuC7023 Bit Value 000 001 010 011 100 101 Other ADCCP Register Name: ADCCP Address: 0xFFFF0504 Default value: 0x00 Access: Read/write Function: ADCCP is an ADC positive channel selection register. This MMR is described in Table 25. Table 25. ADCCP MMR Bit Designation ...

Page 31

... Default Value: 0x00 Access: Read/write Function: ADCRST resets the digital interface of the ADC. Writing any value to this register resets all the ADC registers to their default value. Rev Page ADuC7023 pin. This pin is high during a goes back low. This BUSY ...

Page 32

... ADC0 ADC11 V IN– Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7023 SW2 switches between A (Channel−) and REF The input signal must be chosen so that V CAPACITIVE IN− ...

Page 33

... REF ADC1 Figure 29. Buffering Differential Inputs ), which is dependent upon CM minimum and V maximum values Ranges Min V Max Signal Peak-to-Peak REF CM CM 2.5 V 1.25 V 2.05 V 2.5 V 2.048 V 1.024 V 2.276 V 2.048 V 1.25 V 0.75 V 2.55 V 1.25 V 2.5 V 1.25 V 1.75 V 2.5 V 2.048 V 1.024 V 1.976 V 2.048 V 1.25 V 0.75 V 2. REF ADuC7023 ...

Page 34

... For some users not possible to get such a known pair. For these cases, an ADuC7023 comes with a single point calibration value loaded in the TEMPREF register. For more details on this register, see the TEMPREF Register section. During production testing of the ADuC7023, the TEMPREF register is loaded with an offset adjustment factor ...

Page 35

... TEMREF register not an exact value and must only be used with the TEMPREF register. BAND GAP REFERENCE The ADuC7023 provides an on-chip band gap reference of 2.5 V, which can be used for the ADC and DAC. This internal reference also appears on the V pin. When using the internal REF reference, a 0.47 μ ...

Page 36

... When debugging, user code should not write to the P0.1/P0.2 and P0.3 pins. If user code toggles any of these pins, JTAG debug pods are not able to connect to the ADuC7023. In case this happens, the user should ensure that Flash Address 0x80014 is erased to allow erasing of the part through the I interface ...

Page 37

... Address: 0xFFFFF800 Default value: 0x20 Access: Read Function: FEESTA is a read-only register that reflects the status of the flash control interface as described in Table 30. Rev Page ADuC7023 //Protect Page 4 to Page 7 //16 bit key value //16 bit key value //Write key command FEEADR = . ...

Page 38

... ADuC7023 FEEMOD Register Name: FEEMOD Address: 0xFFFFF804 Default value: 0x0000 Access: Read/write Function: FEEMOD sets the operating mode of the flash control interface. Table 31 shows FEEMOD MMR bit designations. Table 31. FEEMOD MMR Bit Designations Bit Description Reserved. 8 Reserved. Always set this bit to 0. ...

Page 39

... This bit is cleared by the user to protect the pages in writing. This bit is set by the user to allow writing the pages. Command Sequence for Executing a Mass Erase FEEDAT = 0x3CFF; FEEADR = 0xFFC3; FEEMOD = FEEMOD|0x8; FEECON = 0x06; command Rev Page ADuC7023 //Erase key enable //Mass erase ...

Page 40

... ARM mode with 32-bit wide SRAM instead of 16-bit wide Flash/EE memory. Remap Operation When a reset occurs on the ADuC7023, execution automatically starts in factory programmed, internal configuration code. This kernel is hidden and cannot be accessed by user code. If the part is ...

Page 41

... This bit is cleared for the DAC pins and registers to return to their default state. 1 Reserved. Always set This bit is set configure the GPIO pins to retain their state after a watchdog or software reset. This bit is cleared for the GPIO pins and registers to return to their default state. Rev Page ADuC7023 ...

Page 42

... ADuC7023 RSTKEY1 Register Name: RSTKEY1 Address: 0xFFFF0248 Default value: 0xXX Access Write RSTKEY2Register Name: RSTKEY2 Address: 0xFFFF0250 Default value: 0xXX Access: Write Table 38. RSTCFG Write Sequence Name RSTKEY1 RSTCFG RSTKEY2 Rev Page Code 0x76 User value 0xB1 ...

Page 43

... OTHER ANALOG PERIPHERALS DAC The ADuC7023 incorporates four, 12-bit voltage output DACs on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has two selectable ranges gap 2.5 V reference) and The signal range ...

Page 44

... Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 33 get worse as a function of output loading. Most of the ADuC7023 data sheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom of Figure 33 become larger, respectively ...

Page 45

... COMPARATOR supply on the DD supply pin drops The ADuC7023 integrates voltage comparators. The positive input is multiplexed with ADC2, and the negative input has two options: ADC3 or DAC0. The output of the comparator can be configured to generate a system interrupt, be routed directly to the programmable logic array, start an ADC conversion ...

Page 46

... ADuC7023 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 45. CMPCON Register Name: CMPCON Address: 0xFFFF0444 Default value: 0x0000 Access: Read/write Table 45. CMPCON MMR Bit Descriptions Bit Value Name Description Reserved. 10 CMPEN Comparator enable bit. This bit is set by the user to enable the comparator. ...

Page 47

... OSCILLATOR AND PLL—POWER CONTROL Clocking System Each ADuC7023 integrates a 32.768 kHz ± 3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency binary submultiples of it ...

Page 48

... ADuC7023 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 48) and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and the power-down mode, POWCON1 controls the clock ...

Page 49

... I2C0PO I2C0CLKDIV Table 53. POWCON1 Write Sequence Name POWKEY3 POWCON1 POWKEY4 Rev Page ADuC7023 Description Reserved. Clearing this bit powers down the SPI. SPI block driving clock divider bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. Clearing this bit powers 2 down the I C1 ...

Page 50

... GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7023 part enters a power-saving mode, the GPIO pins retain their state. Also note, that by setting RSTCFG bit 0, the GPIO pins can retain their state during a watchdog or software reset ...

Page 51

... Reserved R/W 20 R/W 19 Reserved R(b00) 16 R/W 15 Reserved R(b00) 12 R/W 11 Reserved Rev Page ADuC7023 HIGH DRIVE STRENGTH MEDIUM DRIVE STRENGTH LOW DRIVE STRENGTH HIGH DRIVE STRENGTH MEDIUM DRIVE STRENGTH LOW DRIVE STRENGTH – GP1PAR ...

Page 52

... ADuC7023 Bit GP0PAR GP1PAR R(b00) R(b00) 8 R/W R/W 7 Reserved Reserved R(b00) R(b00) 4 R/W R/W 3 Reserved Reserved R(b00) R(b00) 0 R/W R/W 1 When P2.0 is configured as AIN12, the internal pull-up resistor cannot be disabled. GP0DAT Register Name Address Default Value GP0DAT 0xFFFFF420 0x000000XX GP1DAT 0xFFFFF430 0x000000XX ...

Page 53

... Reserved. SERIAL PERIPHERAL INTERFACE The ADuC7023 integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex maximum bit rate of 20 Mbps. ...

Page 54

... ADuC7023 Table 62. SPISTA MMR Bit Designations Bit Name Description Reserved bits. 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE. ...

Page 55

... Access: Read/write Function: This 8-bit MMR is the SPI baud rate selection register. SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Rev Page ADuC7023 ...

Page 56

... ADuC7023 Table 63. SPICON MMR Bit Designations Bit Name Description SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00 interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received into the FIFO ...

Page 57

... Master mode enable bit. This bit is set by the user to enable master mode. This bit is cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. This bit is set by the user to enable the SPI. This bit is cleared by the user to disable the SPI. Rev Page ADuC7023 ...

Page 58

... FIFOs. Status bits are available to the user to control these FIFOs. CONFIGURING EXTERNAL PINS FOR I FUNCTIONALITY 2 The I C pins of the ADuC7023 device are P0.4 and P0.5 for I 2 and P0.6 and P0.7 for I C1. 2 P0.4 and P0.6 are the I C clock signals and P0.5 and P0.7 are the ...

Page 59

... C master receives a no acknowledge master has lost in trying to gain control of the master has transmitted a byte master receives data master is receiving data bus becomes free master mode master mode. RevPrI| Page ADuC7023 2 C bus bus. ...

Page 60

... ADuC7023 Master Status Registers, I2CxMSTA Name: I2C0MSTA , I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default value: 0x0000, 0x0000 Access: Read Function: These 16-bit MMRs are the I Table 65. I2CxMSTA MMR Bit Designations Bit Name Description Reserved. These bits are reserved I2CBBUSY I C bus busy status bit. ...

Page 61

... Table 68. I2CxADR0 MMR in 10-Bit Address Mode Bit Rev Page ADuC7023 I2C0MCNT1, I2C1MCNT1 0xFFFF0814, 0xFFFF0914 0x00, 0x00 Read These 8-bit MMRs hold the number of bytes received thus far during a read sequence with a slave device. I2C0ADR0, I2C1ADR0 ...

Page 62

... ADuC7023 Address 1 Registers, I2CxADR1 Name: I2C0ADR1, I2C1ADR1 Address: 0xFFFF081C , 0xFFFF091C Default value: 0x00 Access: Read/write Function: These 8-bit MMRs are used in 10-bit addressing mode only. These registers contain the least significant byte of the address. Table 69. I2CxADR1 MMR in 10-Bit Address Mode ...

Page 63

... This is a broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately ...

Page 64

... ADuC7023 Table 72. I2CxSSTA MMR Bit Designations Bit Name Description 15 Reserved bit. 14 I2CSTA This bit is set to 1 if: A start condition followed by a matching address is detected also set if a start byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received. ...

Page 65

... I C Common Registers FIFO Status Registers, I2CxFSTA Name: Address: Default value: Access: Function: Rev Page ADuC7023 I2C0IDx, I2C1IDx 0xFFFF093C = I2C1ID0 0xFFFF083C = I2C0ID0 0xFFFF0940 = I2C1ID1 0xFFFF0840 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF0844 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF0848 = I2C0ID3 0x00 Read/write These 8-bit MMRs are programmed with I 2 bus IDs of the slave ...

Page 66

... Figure 39. PLA Element In total, 20 GPIO pins are available on the ADuC7023 for the PLA. These include 11 input pins and nine output pins, which need to be configured in the GPxCON register as PLA pins before using the PLA. The PLA is configured via a set of user MMRs. The output(s) of ...

Page 67

... This bit is set by the user to select the input pin of the particular element. This bit is cleared by the user to select the output of Mux 1. Look-up table control. 0. NOR. B and not A. Not A. A and not B. Not B. EXOR. NAND. AND. EXNOR. B. Not not B. OR. 1. Rev Page ADuC7023 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...

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... ADuC7023 Bit Value 0 PLACLK Register Name: PLACLK Address: 0xFFFF0B40 Default value: 0x00 Access: Read/write Function: PLACLK is the clock selection for the flip- flops. The maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 77. PLACLK MMR Bit Descriptions ...

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... PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Rev Page ADuC7023 PLAELM9 to PLAELM15 Element 8 Element 10 Element 12 Element 14 Element 9 ...

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... ADuC7023 PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW The ADuC7023 integrates a 5-channel pulse-width modulator (PWM) interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins ...

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... Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs H-bridge mode, HMODE = 1. See Table 85 to determine the PWM outputs. 1 Rev Page ADuC7023 ) is low, the TRIPINPUT ...

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... ADuC7023 On power-up, PWMCON1 defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 85). Clear the PWM trip interrupt by writing any value to the PWMCLRI Table 85. PWM Output Selection PWMCON1 MMR ENA HOFF POINV ...

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... PWM1LEN Register Name: PWM1LEN Address: 0xFFFF0FA0 Default value: 0x0000 Access: Read and write Function: PWM3 output pin goes high when the PWM timer reaches the value stored in this register. Rev Page ADuC7023 ...

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... ADuC7023 PWM2COM0 Compare Register Name: PWM2COM0 Address: 0xFFFF0FA4 Default value: 0x0000 Access: Read/write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2COM1 Compare Register Name: PWM2COM1 Address: 0xFFFF0FA8 Default value: 0x0000 Access: ...

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... PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 22 interrupt sources on the ADuC7023 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC. Four additional interrupt sources are generated from external interrupt request pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ...

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... ADuC7023 IRQEN Register Name: IRQEN Address: 0xFFFF0008 Default value: 0x00000000 Access: Read/write Function: IRQEN provides the value of the current enable mask. When each bit is set to 1, the source request is enabled to create an IRQ exception. When each bit is set to 0, the source request is disabled or masked, which does not create an IRQ exception ...

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... PRIORITY ACTIVE IRQ Figure 41. Interrupt Structure VECTORED INTERRUPT CONTROLLER (VIC) The ADuC7023 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. ...

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... ADuC7023 IRQVEC Register The IRQ interrupt vector register, IRQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. ...

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... IRQ2PI A priority level can be set for IRQ2. 7 Reserved Reserved bit PLA0PI A priority level can be set for PLA IRQ0. 3 Reserved Reserved bit IRQ1PI A priority level can be set for IRQ1. Rev Page ADuC7023 ...

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... ADuC7023 IRQCONN Register The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts and the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, then FIQs and IRQs may still be used, but it is not possible to nest IRQs or FIQs ...

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... When this bit is cleared, it means no nesting or prioritization of FIQs is allowed. External Interrupts and PLA interrupts The ADuC7023 provides up to four external interrupt sources and two PLA interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source or the PLA interrupt source, the appropriate bit must be set in the FIQEN or IRQEN register ...

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... Reserved These bits are reserved and should not be 0 written to. TIMERS The ADuC7023 has three general-purpose timer/counters: Timer0, Timer1, and Timer2 or Watchdog Timer. These three timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale and starts again at the minimum value ...

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... T1VAL is a 32-bit read-only register that represents the current state of the counter. T1CON Register Name: T1CON Address: 0xFFFF0328 Default value: 0x00000000 Access: Read/write T1CON is the configuration MMR described in Table 101. Rev Page ADuC7023 32-BIT LOAD 32-BIT TIMER1 IRQ UP/DOWN COUNTER ADC CONVERSION TIMER1 VALUE CAPTURE ...

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... ADuC7023 Table 101. T1CON MMR Bit Descriptions Bit Value Description Reserved. 17 Event select bit. This bit is set by the user to enable time capture of an event. This bit is cleared by the user to disable time capture of an event Event select range 31. These events are as described in Table 87 ...

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... Write T2CLRI is an 8-bit register. Writing any value to this register on successive occassions clears the Timer2 interrupt in normal mode or resets a new timeout period in watchdog mode . The user must perform successive writes to this register to ensure resetting the timeout period. Rev Page ADuC7023 ...

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... ADuC7023 Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T2CLRI to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = shown in Figure 45 ...

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... Linear Voltage Regulator DD Each ADuC7023 requires a single 3.3 V supply, but the core logic requires a 2.6 V supply. An on-chip linear regulator generates the 2.6 V from IOV is the 2.6 V supply for the core logic. An external compensation capacitor of 0.47 μ F must be connected between LV 1.6V DGND (as close as possible to these pins) to act as a tank of 10µ ...

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... In these cases, tie all the ADuC7023 AGND and DGND pins to the analog ground plane, as illustrated in Figure 50b. In systems with only one ground plane, ensure that ...

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... POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7023. For LV below 2.40 V typical, the internal POR DD holds the part in reset rises above 2. internal DD timer times out for typically 64 ms before the part is released from reset. The user must ensure that the power supply IOV has reached a stable 2 ...

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... ADuC7023 TYPICAL SYSTEM CONFIGURATION A typical ADuC7023 configuration is shown in Figure 54. It summarizes some of the hardware considerations. The bottom of the LFCSP package has an exposed pad that needs to be soldered to a metal plate on the board for mechanical reasons. The metal plate of the board can be connected to ground. ...

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... Hardware The hardware sytsem uses the ADuC7023 evaluation board, aserial port programming cable, and a RDI-compliant JTAG emulator (included in the ADuC7023 QuickStart Plus only). Software The software system has an integrated development environment, incorporating an assembler, compiler, and nonintrusive JTAG-based debugger ...

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... ADuC7023 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE 6.10 0.30 6.00 SQ 0.23 5.90 0. 0.50 BSC 21 20 0.45 TOP VIEW BOTTOM VIEW 0.40 0.35 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. Figure 55. 40-Lead Frame Chip Scale Package [LFCSP_WQ Body, Very Thin Quad (CP-40-10) Dimensions shown in millimeters 5 ...

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... ADuC7023 Package Package Ordering Description Option Quantity 40-Lead CP-40-10 490 LFCSP_WQ 40-Lead CP-40-10 2,500 LFCSP_WQ 32-Lead CP-32-10 750 LFCSP_WQ 32-Lead CP-32-11 490 LFCSP_WQ 32-Lead CP-32-11 5,000 LFCSP_WQ 32-Lead CP-32-11 1,500 LFCSP_WQ ADuC7023 QuickStart Plus Development System Using 32-Pin ADuC7023 ADuC7023 QuickStart Plus Development System Using 40-Pin ADuC7023 ...

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... ADuC7023 NOTES Rev Page ...

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... NOTES Rev Page ADuC7023 ...

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... ADuC7023 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08675-0-7/10(B) Rev Page ...

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