ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 36

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
NONVOLATILE FLASH/EE MEMORY
The ADuC7023 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit reprogram-
mable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
The Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7023, Flash/EE memory technology allows the user to
update program code space in-circuit, without needing to
replace one-time programmable (OTP) devices at remote
operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The
lower 62 kB are available to the user, and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1.
2.
3.
4.
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of −40° to +125°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit
J
= 85°C). As part of this qualification procedure, the
Initial page erase sequence.
Read/verify sequence (single Flash/EE).
Byte program sequence memory.
Second read/verify sequence (endurance cycle).
Rev. B | Page 36 of 96
before data retention is characterized. This means that the
Flash/EE memory is guaranteed to retain its data for its fully
specified retention lifetime every time the Flash/EE memory is
reprogrammed. In addition, note that retention lifetime, based
on activation energy of 0.6 eV, derates with T
Figure 30.
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in circuit,
using the serial download mode or the provided JTAG mode.
Downloading (In-Circuit Programming) via I
The ADuC7023 facilitates code download via the the I
The parts enter download mode after a reset or power cycle if
the BM pin is pulled low through an external 1 kΩ resistor and
Flash Addess 0x80014 = 0xFFFFFFFF. Once in download mode,
the user can download code to the full 62 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC I
of the development system for serial downloading via the I
USB to I
Devices, Inc. This board connects to the USB port of a PC and
to the I
I2C/LIN-CONV-Z.
The
downloading via the I
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
To access the part via the JTAG interface, the P0.0/BM pin must
be set high to enable P0.1/P0.2/P0.3 as JTAG pins.
When debugging, user code should not write to the P0.1/P0.2
and P0.3 pins. If user code toggles any of these pins, JTAG
debug pods are not able to connect to the ADuC7023. In case
this happens, the user should ensure that Flash Address
0x80014 is erased to allow erasing of the part through the I
interface.
AN-806
600
450
300
150
2
C port of the ADuC7023. The part number is USB-
0
2
C download dongle can be purchased from Analog
30
Application Note describes the protocol for serial
Figure 30. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
2
55
C in more detail.
70
2
C download is provided as part
85
100
125
J
as shown in
135
2
C
2
150
C port.
2
2
C. A
C