ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 80

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts and the other to enable nesting
and prioritization of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs may still be used,
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
Address:
Default value:
Access:
Table 94. IRQCONN MMR Bit Designations
Bit
31 to 2
1
0
IRQSTAN Register
If IRQCONN Bit 0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depends on the
priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts. If
the IRQ is of Priority 1, then Bit 1 asserts, and so forth. When a
bit is set in this register, all interrupts of that priority and lower
are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08, and writing 0xFF a second time
changes the register to 0x00.
Name:
Address:
Default value:
Access:
Name
ENFIQN
ENIRQN
Reserved
IRQCONN
0xFFFF0030
0x00000000
Read and write
IRQSTAN
0xFFFF003C
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
This bit is set to 1 to enable nesting of FIQ
interrupts.
This bit is cleared to mean no nesting or
prioritization of FIQs is allowed.
This bit is set to 1 to enable nesting of IRQ
interrupts.
When this bit is cleared, it means no
nesting or prioritization of IRQs is
allowed.
Rev. B | Page 80 of 96
Table 95. IRQSTAN MMR Bit Designations
Bit
31 to 8
7 to 0
FIQVEC Register
The FIQ interrupt vector register, FIQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
Address:
Default value:
Access:
Table 96. FIQVEC MMR Bit Designations
Bit
31 to 23
22 to 7
6 to 2
1 to 0
FIQSTAN Register
If IRQCONN Bit 1 is asserted and FIQVEC is read, then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts. If the FIQ
is of Priority 1, then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
Name
Reserved
Type
Read only
R/W
Reserved
FIQVEC
0xFFFF011C
0x00000000
Read only
Description
These bits are reserved and should not be
written to.
This bit is set to 1 to enable nesting of FIQ
interrupts.
When this bit is cleared, it means no
nesting or prioritization of FIQs is
allowed.
Initial
Value
0
0
0
0
Description
Always read as 0.
IRQBASE register value.
Highest priority source. This
is a value between 0 and 27
that represents the possible
interrupt sources. For
example, if the highest
currently active FIQ is
Timer 2, then these bits are
[00100].
Reserved bits.