ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 66

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
Table 73. I2CxFSTA MMR Bit Designations
Bit
15 to 10
9
8
7 to 6
5 to 4
3 to 2
1 to 0
Name
I2CFMTX
I2CFSTX
I2CMRXSTA
I2CMTXSTA
I2CSRXSTA
I2CSTXSTA
Description
Reserved bits.
This bit is set to 1 to flush the master
Tx FIFO.
This bit is set to 1 to flush the slave Tx
FIFO.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
I
[00] = FIFO empty
[01] = byte written to FIFO
[10] = 1 byte in FIFO
[11] = FIFO full
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
2
2
2
2
C master receive FIFO status bits.
C master transmit FIFO status bits.
C slave receive FIFO status bits.
C slave transmit FIFO status bits.
Rev. B | Page 66 of 96
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7023 integrates a fully programmable logic array
(PLA) consisting of sixteen PLA elements.
Each PLA element contains a two-input look-up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 39.
In total, 20 GPIO pins are available on the ADuC7023 for the
PLA. These include 11 input pins and nine output pins, which
need to be configured in the GPxCON register as PLA pins before
using the PLA.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONV
eight PLA output pins.
Table 74. Element Input/Output
Element
0
1
2
3
4
5
6
7
1
Internal pins only. Read via GPxDAT register.
START
PLA Block 0
signal of the ADC, to an MMR, or to any of the
Input
P0.4
P0.5
P0.6
P1.2
P1.3
P1.6
P1.7
P2.0
0
1
2
3
Output
P0.7
P1.0
P1.1
P1.4
P1.5
P2.1
P2.2
P2.3
Figure 39. PLA Element
A
B
1
LOOK-UP
TABLE
Element
8
9
10
11
12
13
14
15
PLA Block 1
Input
P0.0
P0.1
P2.4
NC
NC
NC
NC
NC
4
Output
P0.2
P0.3
P2.5
NC
NC
NC
NC
NC
1