ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 56

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
Table 63. SPICON MMR Bit Designations
Bit
15 to 14
13
12
11
10
9
8
7
6
5
4
3
2
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPIOEN
SPIROW
SPIZEN
SPITMDE
SPILF
SPIWOM
SPICPO
SPICPH
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have
been received into the FIFO.
[11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full or four
bytes present.
SPI Tx FIFO flush enable bit.
This bit is set to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
This bit is cleared to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
This bit is set to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set, all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
This bit is cleared to disable Rx FIFO flushing.
Continuous transfer enable.
This bit is set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the Tx register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is
empty.
This bit is cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.
Loop back enable bit.
This bit is set by the user to connect MISO to MOSI and test software.
This bit is cleared by the user to be in normal mode.
Slave MISO output enable bit.
This bit is set for MISO to operate as normal.
This bit is cleared to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.
SPIRX overflow overwrite enable.
This bit is set by the user; the valid data in the Rx register is overwritten by the new serial byte received.
This bit is cleared by the user; the new serial byte received is discarded.
SPI transmit zeros when Tx FIFO is empty.
This bit is set to transmit 0x00 when there is no valid data in the Tx FIFO.
This bit is cleared to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
This bit is set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
This bit is cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
LSB first transfer enable bit.
This bit is set by the user; the LSB is transmitted first.
This bit is cleared by the user; the MSB is transmitted first.
SPI wired or mode enable bit.
This bit is set to 1 enable open-drain data output. External pull-ups are required on data out pins.
This bit is cleared for normal output levels.
Serial clock polarity mode bit.
This bit is set by the user; the serial clock idles high.
This bit is cleared by the user; the serial clock idles low.
Serial clock phase mode bit.
This bit is set by the user; the serial clock pulses at the beginning of each serial bit transfer.
This bit is cleared by the user; the serial clock pulses at the end of each serial bit transfer.
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