ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 44

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
AV
lower nonlinearity is similar. However, the upper portion of the
transfer function follows the ideal line right to the end (V
case, not AV
The endpoint nonlinearities conceptually illustrated in
Figure 33 get worse as a function of output loading. Most
of the ADuC7023 data sheet specifications assume a 5 kΩ
resistive load to ground at the DAC output. As the output is
forced to source or sink more current, the nonlinear regions at
the top or bottom of Figure 33 become larger, respectively. With
larger current demands, this can significantly limit output
voltage swing.
References to ADC and the DACs
ADC and DACs can be configured to use internal V
external reference as a reference source. Internal V
work with an external 0.47 μF capacitor.
Table 41. Reference Source Selection for ADC and DAC
REFCON Bit 0
0
0
0
0
1
1
1
1
DD
mode only. In 0-to-V
Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation
AV
DD
– 100mV
DD
100mV
), showing no signs of endpoint linearity errors.
AV
DD
DACxCON[1:0]
00
01
10
11
00
01
10
11
0x00000000
REF
mode (with V
Reserved.
Reserved.
Description
ADC works with external
reference. DACs power
down.
ADC works with external
reference. DACs work with
internal AV
ADC works with internal
V
ADC and DACs work with an
external reference. The
external reference must be
capable of overdriving the
internal reference.
ADC and DACs work with
internal V
ADC works with internal
V
internal AV
REF
REF
. DACs power down.
. DACs work with
REF
REF
0x0FFF0000
DD
DD
< AV
.
.
.
REF
REF
DD
must
), the
or an
REF
in this
Rev. B | Page 44 of 96
Configuring DAC Buffers in Op Amp Mode
In op amp mode, the DAC output buffers are used as an op amp
with the DAC itself disabled.
If DACBCFG Bit 0 is set, ADC0 is the positive input to the op
amp, ADC1 is the negative input, and DAC0 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC0CON.
If DACBCFG Bit 1 is set, ADC2 is the positive input to the op
amp, ADC3 is the negative input, and DAC1 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC1CON.
If DACBCFG Bit 2 is set, ADC4 is the positive input to the op
amp, ADC5 is the negative input, and DAC2 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC2CON.
If DACBCFG Bit 3 is set, ADC8 is the positive input to the op
amp, ADC9 is the negative input, and DAC3 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC3CON.
DACBCFG Register
Name:
Address:
Default value:
Access:
Table 42. DACBCFG MMR Bit Designations
Bit
7 to 4
3
2
1
0
Description
Reserved. Always set to 0.
This bit is set to 1 to configure DAC3 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
This bit is set to 1 to configure DAC2 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
This bit is set to 1 to configure DAC1 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
This bit is set to 1 to configure DAC0 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
DACBCFG
0xFFFF0654
0x00
Read/write