ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 84

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
Table 101. T1CON MMR Bit Descriptions
Bit
31 to 18
17
16 to 12
11 to 9
8
7
6
5 to 4
3 to 0
T1CLRI Register
Name:
Address:
Default value:
Access:
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
Value
000
001
010
011
00
01
10
11
0000
0100
1000
1111
T1CLRI
0xFFFF032C
0xXX
Write
Description
Reserved.
Event select bit.
This bit is set by the user to enable time
capture of an event.
This bit is cleared by the user to disable
time capture of an event.
Event select range, 0 to 31. These events
are as described in Table 87. All events are
offset by two, that is, Event 2 in Table 87
becomes Event 0 for the purposes of
Timer1.
Clock select.
Core clock (HCLK).
Internal 32.768 kHz crystal
UCLK
P1.1 raising edge triggered.
Count up.
This bit is set by the user for Timer1 to
count up.
This bit is cleared by the user for Timer1
to count down by default.
Timer1 enable bit.
This bit is set by the user to enable
Timer1. This bit is cleared by the user to
disable Timer1 by default.
Timer1 mode.
This bit is set by the user to operate in
periodic mode.
This bit is cleared by the user to operate in
free-running mode. Default mode.
Format.
Binary.
Reserved.
Hours, minutes, seconds, hundredths
(23 hours to 0 hour).
Hours, minutes, seconds, hundredths
(255 hours to 0 hour).
Prescale.
Source clock/1.
Source clock/16.
Source clock/256.
Source clock/32,768.
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T1CAP Register
Name:
Address:
Default value:
Access:
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurrs. This event must be
selected in T1CON.
Timer2 (Watchdog Time)
Timer2 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. When enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Normal Mode
Timer2 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 44).
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in the T2CON MMR.
Timer2 decreases from the value present in the T2LD register
until 0. T2LD is used as the timeout. The maximum timeout can
be 512 sec using the prescaler/256, and full-scale in T2LD.
Timer3 is clocked by the internal 32 kHz crystal when operating
in the watchdog mode. To enter watchdog mode successfully,
Bit 5 in the T2CON MMR must be set after writing to the
T2LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T2CON register. To avoid reset or interrupt,
any value must be written to T2CLRI before the expiration
period. This reloads the counter with T2LD and begins a new
timeout period.
When watchdog mode is entered, T2LD and T2CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer2 to exit
watchdog mode.
The Timer2 interface consists of four MMRs: T2LD, T2VAL,
T2CON, and T2CLRI.
32.768kHz
1, 4, 16, OR 256
PRESCALER
Figure 44. Timer2 Block Diagram
T1CAP
0xFFFF0330
0x00000000
Read
COUNTER
UP/DOWN
TIMER2
VALUE
16-BIT
16-BIT
LOAD
WATCHDOG RESET
TIMER2 IRQ