ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 51

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

Table 79. PWM Output Selection
ENA
0
X
1
1
1
1
1
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 80).
Table 80. Compare Registers
Name
PWM1COM1
PWM1COM2
PWM1COM3
PWM2COM1
PWM2COM2
PWM2COM3
PWM3COM1
PWM3COM2
PWM3COM3
The PWM trip interrupt can be cleared by writing any value to
the PWMICLR MMR. Note that when using the PWM trip
interrupt, users should make sure that the PWM interrupt
has been cleared before exiting the ISR. This prevents genera-
tion of multiple interrupts.
PWM CONVERT START CONTROL
The PWM can be configured to generate an ADC convert start
signal after the active low-side signal goes high. There is a program-
mable delay between when the low-side signal goes high and
the convert start signal is generated.
This is controlled via the PWMCON2 MMR. If the delay
selected is higher than the width of the PWM pulse, the
interrupt remains low.
X = don’t care, HS = high side, LS = low side.
PWMCON1 MMR
HOFF
0
1
0
0
0
0
POINV
X
X
0
0
1
1
Address
0xFFFF0F84
0xFFFF0F88
0xFFFF0F8C
0xFFFF0F94
0xFFFF0F98
0xFFFF0F9C
0xFFFF0FA4
0xFFFF0FA8
0xFFFF0FAC
DIR
X
X
0
1
0
1
PWM1
1
1
0
HS
HS
1
Default Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
1
PWM2
1
0
0
LS
LS
1
PWM Outputs
PWM3
1
1
HS
0
1
HS
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM4
1
0
LS
0
1
LS
Rev. 0 | Page 51 of 96
Table 81. PWMCON2 MMR Bit Designations
(Address = 0xFFFF0FB4, Default Value = 0x00)
Bit
7
3:0
When calculating the time from the convert start delay to the
start of an ADC conversion, the user needs to take account of
internal delays. The example in Figure 33 shows the case for a
delay of four clocks. One additional clock is required to pass the
convert start signal to the ADC logic. When the ADC logic
receives the convert start signal, an ADC conversion begins on
the next ADC clock edge (see Figure 33).
UCLK/ADC_CLOCK
SIGNAL PASSED
TO ADC LOGIC
PWM SIGNAL
Value
1
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TO CONVST
LOW SIDE
COUNT
Name
CSEN
CSD3
Figure 33. ADC Conversion
Description
Convert start enable.
Set to 1 by the user to enable the PWM
to generate a convert start signal.
Cleared by the user to disable the PWM
convert start signal.
Convert start delay. Delays the convert
start signal by a number of clock pulses.
4 clock pulses.
8 clock pulses.
12 clock pulses.
16 clock pulses.
20 clock pulses.
24 clock pulses.
28 clock pulses.
32 clock pulses.
36 clock pulses.
40 clock pulses.
44 clock pulses.
48 clock pulses.
52 clock pulses.
56 clock pulses.
60 clock pulses.
64 clock pulses.
ADuC7122