ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 66

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Bit
7
6
5
4
3
2
1
0
Name
I2CGC
I2CSBUSY
I2CSNA
I2CSRxFO
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
Description
I
This bit is set to 1 if the slave receives a general call command of any type.
If the command received is a reset command, then all registers return to their default state.
If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can
be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
I
Set to 1 when the slave receives a start condition.
Cleared by hardware if the received address does not match any of the I2CxIDx registers, if the slave device receives
a stop condition, or if a repeated start address does not match any of the I2CxIDx registers.
I
This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if NACK is returned
because there is no data in the Tx FIFO or if the I2CNACKEN bit is set in the I2CxSCTL register.
This bit is cleared in all other conditions.
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2C slave receive request bit.
This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in
I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
I
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the read bit
transmission.
This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
I
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the
rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
I
If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the write bit
transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
2
2
2
2
2
2
C general call status bit.
C slave busy status bit.
C slave NACK data bit.
C slave transmit request bit.
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
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